From patchwork Tue Oct 2 15:36:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 188555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A8D462C008C for ; Wed, 3 Oct 2012 01:39:08 +1000 (EST) Received: from localhost ([::1]:40682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJ4Ys-0000wq-OK for incoming@patchwork.ozlabs.org; Tue, 02 Oct 2012 11:39:06 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJ4YX-0000XM-Dz for qemu-devel@nongnu.org; Tue, 02 Oct 2012 11:38:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJ4YM-0000TM-NX for qemu-devel@nongnu.org; Tue, 02 Oct 2012 11:38:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:17166) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJ4YM-0000TC-Dk for qemu-devel@nongnu.org; Tue, 02 Oct 2012 11:38:34 -0400 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q92FbfTo016692 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 2 Oct 2012 11:37:41 -0400 Received: from dell-pet610-01.lab.eng.brq.redhat.com (dell-pet610-01.lab.eng.brq.redhat.com [10.34.42.20]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q92FbKHq021344; Tue, 2 Oct 2012 11:37:38 -0400 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Tue, 2 Oct 2012 17:36:57 +0200 Message-Id: <1349192235-31895-6-git-send-email-imammedo@redhat.com> In-Reply-To: <1349192235-31895-1-git-send-email-imammedo@redhat.com> References: <1349192235-31895-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: aliguori@us.ibm.com, hpa@linux.intel.com, ehabkost@redhat.com, jan.kiszka@siemens.com, Don@cloudswitch.com, mtosatti@redhat.com, mdroth@linux.vnet.ibm.com, blauwirbel@gmail.com, avi@redhat.com, pbonzini@redhat.com, akong@redhat.com, lersek@redhat.com, afaerber@suse.de, stefanha@linux.vnet.ibm.com Subject: [Qemu-devel] [PATCH 05/23] target-i386: move out CPU features initialization in separate func X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org later it could be used in cpu_x86_find_by_name() to init CPU from found cpu_def Signed-off-by: Igor Mammedov Reviewed-by: Eduardo Habkost --- v2: - rebased on top of "i386: cpu: remove duplicate feature names" http://www.mail-archive.com/qemu-devel@nongnu.org/msg129458.html --- target-i386/cpu.c | 84 +++++++++++++++++++++++++++------------------------- 1 files changed, 44 insertions(+), 40 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index ad831a0..3b7bdbd 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1097,6 +1097,49 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque, cpu->env.tsc_khz = value / 1000; } +static void cpudef_2_x86_cpu(X86CPU *cpu, x86_def_t *def, Error **errp) +{ + CPUX86State *env = &cpu->env; + + if (def->vendor1) { + env->cpuid_vendor1 = def->vendor1; + env->cpuid_vendor2 = def->vendor2; + env->cpuid_vendor3 = def->vendor3; + } else { + env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; + env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; + env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; + } + env->cpuid_vendor_override = def->vendor_override; + object_property_set_int(OBJECT(cpu), def->level, "level", errp); + object_property_set_int(OBJECT(cpu), def->family, "family", errp); + object_property_set_int(OBJECT(cpu), def->model, "model", errp); + object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp); + object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp); + object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); + object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000, + "tsc-frequency", errp); + env->cpuid_features = def->features; + env->cpuid_ext_features = def->ext_features; + env->cpuid_ext2_features = def->ext2_features; + env->cpuid_ext3_features = def->ext3_features; + env->cpuid_kvm_features = def->kvm_features; + env->cpuid_svm_features = def->svm_features; + env->cpuid_ext4_features = def->ext4_features; + env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features; + env->cpuid_xlevel2 = def->xlevel2; + + /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on + * CPUID[1].EDX. + */ + if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && + env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && + env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) { + env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES; + env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES); + } +} + static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def, const char *cpu_model, Error **errp) { @@ -1367,7 +1410,6 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) int cpu_x86_register(X86CPU *cpu, const char *cpu_model) { - CPUX86State *env = &cpu->env; x86_def_t def1, *def = &def1; Error *error = NULL; @@ -1377,45 +1419,7 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_model) goto out; } - if (def->vendor1) { - env->cpuid_vendor1 = def->vendor1; - env->cpuid_vendor2 = def->vendor2; - env->cpuid_vendor3 = def->vendor3; - } else { - env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; - env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; - env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; - } - env->cpuid_vendor_override = def->vendor_override; - object_property_set_int(OBJECT(cpu), def->level, "level", &error); - object_property_set_int(OBJECT(cpu), def->family, "family", &error); - object_property_set_int(OBJECT(cpu), def->model, "model", &error); - object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error); - env->cpuid_features = def->features; - env->cpuid_ext_features = def->ext_features; - env->cpuid_ext2_features = def->ext2_features; - env->cpuid_ext3_features = def->ext3_features; - object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error); - env->cpuid_kvm_features = def->kvm_features; - env->cpuid_svm_features = def->svm_features; - env->cpuid_ext4_features = def->ext4_features; - env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features; - env->cpuid_xlevel2 = def->xlevel2; - object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000, - "tsc-frequency", &error); - - /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on - * CPUID[1].EDX. - */ - if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && - env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && - env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) { - env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES; - env->cpuid_ext2_features |= (def->features & CPUID_EXT2_AMD_ALIASES); - } - - - object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error); + cpudef_2_x86_cpu(cpu, def, &error); out: if (error) {