From patchwork Sun Sep 30 01:32:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 188277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A7C172C00E3 for ; Mon, 1 Oct 2012 22:02:41 +1000 (EST) Received: from localhost ([::1]:33100 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TIehr-00084M-QG for incoming@patchwork.ozlabs.org; Mon, 01 Oct 2012 08:02:39 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TIehh-00083y-UT for qemu-devel@nongnu.org; Mon, 01 Oct 2012 08:02:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TIehd-0007BK-Sa for qemu-devel@nongnu.org; Mon, 01 Oct 2012 08:02:29 -0400 Received: from cantor2.suse.de ([195.135.220.15]:59782 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TIehd-0007BE-MD; Mon, 01 Oct 2012 08:02:25 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id C2699A0FF5; Mon, 1 Oct 2012 14:02:24 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Sun, 30 Sep 2012 03:32:38 +0200 Message-Id: <1348968759-10913-1-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , Riku Voipio , "qemu-ppc@nongnu.org List" Subject: [Qemu-devel] [PATCH 1/2] linux-user: ppc: mark as long long aligned X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The PPC32 ABI dictates that long long (64bit) parameters are pass in odd/even register pairs. Because unlike ARM and MIPS we start at an odd register number, we can reuse the same aligning code that ARM and MIPS use. Signed-off-by: Alexander Graf --- linux-user/syscall.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 1a38169..8cd56f2 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -587,12 +587,16 @@ extern int setfsgid(int); extern int setgroups(int, gid_t *); /* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers */ -#ifdef TARGET_ARM +#ifdef TARGET_ARM static inline int regpairs_aligned(void *cpu_env) { return ((((CPUARMState *)cpu_env)->eabi) == 1) ; } #elif defined(TARGET_MIPS) static inline int regpairs_aligned(void *cpu_env) { return 1; } +#elif defined(TARGET_PPC) && !defined(TARGET_PPC64) +/* PPC32 expects 64bit parameters to be passed on odd/even pairs of registers + which translates to the same as ARM/MIPS, because we start with r3 as arg1 */ +static inline int regpairs_aligned(void *cpu_env) { return 1; } #else static inline int regpairs_aligned(void *cpu_env) { return 0; } #endif