From patchwork Sun Sep 30 16:43:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Endo X-Patchwork-Id: 188172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 966D22C00B9 for ; Mon, 1 Oct 2012 02:44:03 +1000 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Message-ID:Subject:From:To:Date:Content-Type:Mime-Version:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=tQDaVdtOWOOmC/czXSrEJPk1ajPqgbL5NVCm+CvOe0S2uP+CPewO3NGD6WLeB4 Uu59WhtwfZlMdQztp0AdYQWXq6gIccCRWhX7h05NIk2VaIYS2vtk53F43yShaMd0 y5qFaJDx6SilnYmUJHSKbWSwbHXsKM83LPsBHuZNwJ4f0=; Received: (qmail 25800 invoked by alias); 30 Sep 2012 16:43:55 -0000 Received: (qmail 25784 invoked by uid 22791); 30 Sep 2012 16:43:47 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_HOSTKARMA_NO, RP_MATCHES_RCVD, SARE_HTML_INV_TAG, TW_MZ, TW_QD, TW_SR, TW_ZD, UNPARSEABLE_RELAY X-Spam-Check-By: sourceware.org Received: from mailout03.t-online.de (HELO mailout03.t-online.de) (194.25.134.81) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 30 Sep 2012 16:43:33 +0000 Received: from fwd50.aul.t-online.de (fwd50.aul.t-online.de ) by mailout03.t-online.de with smtp id 1TIMc6-0002UU-GQ; Sun, 30 Sep 2012 18:43:30 +0200 Received: from [192.168.0.100] (bjam5MZp8h3NUA3WQOUCu5fpwbl+gJIU68hePIMN5oU6Tv5MoV63byK5qZodZ07ZyZ@[93.218.188.130]) by fwd50.t-online.de with esmtp id 1TIMc1-23xW1g0; Sun, 30 Sep 2012 18:43:25 +0200 Message-ID: <1349023404.9306.63.camel@yam-132-YW-E178-FTW> Subject: [SH] PR 50457 - Add additional atomic models From: Oleg Endo To: gcc-patches Date: Sun, 30 Sep 2012 18:43:24 +0200 Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello, This implements the changes as proposed PR, albeit with some small differences: * I decided to go for a more verbose option name '-matomic-model' instead of just '-matomic'. * In addition to the soft-tcb model I've also added a soft-imask model. Interrupt-flipping atomics might not be the best choice but it is easy to setup and get started with. * There is a new atomic model parameter 'strict' to prohibit mixing of atomic model sequences on SH4A. There are no functional changes to the already existing soft and hard atomics, except that '-msoft-atomic' is now mapped to '-matomic-model=soft-gusa' and '-mhard-atomic' has been removed. Tested on rev 191865 with 'make all' and 'make info dvi pdf' and by compiling a couple of functions that use atomics and eyeballing the asm output. OK? Cheers, Oleg ChangeLog: PR target/50457 * config/sh/sh.opt (matomic-model): New option. (msoft-atomic): Mark as deprecated and alias to matomic-model=soft-gusa. (mhard-atomic): Delete. * config/sh/predicates.md (gbr_displacement): New predicate. * config/sh/sh-protos.h (sh_atomic_model): New struct. (selected_atomic_model): New declaration. (TARGET_ATOMIC_ANY, TARGET_ATOMIC_STRICT, TARGET_ATOMIC_SOFT_GUSA, TARGET_ATOMIC_HARD_LLCS, TARGET_ATOMIC_SOFT_TCB, TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX, TARGET_ATOMIC_SOFT_IMASK): New macros. * config/sh/linux.h (SUBTARGET_OVERRIDE_OPTIONS): Adapt setting to default atomic model. * config/sh/sh.c (selected_atomic_model_): New global variable. (selected_atomic_model, parse_validate_atomic_model_option): New functions. (sh_option_override): Replace atomic selection checks with call to parse_validate_atomic_model_option. * config/sh/sh.h (TARGET_ANY_ATOMIC, UNSUPPORTED_ATOMIC_OPTIONS, UNSUPPORTED_HARD_ATOMIC_CPU): Delete. (DRIVER_SELF_SPECS): Remove atomic checks. config/sh/sync.md: Update documentation comments. (atomic_compare_and_swap, atomic_exchange, atomic_fetch_, atomic_fetch_nand, atomic__fetch, atomic_nand_fetch): Use TARGET_ATOMIC_ANY as condition. Add TARGET_ATOMIC_STRICT check for SH4A case. Handle new TARGET_ATOMIC_SOFT_TCB and TARGET_ATOMIC_SOFT_IMASK cases. (atomic_test_and_set): Handle new TARGET_ATOMIC_SOFT_TCB and TARGET_ATOMIC_SOFT_IMASK cases. (atomic_compare_and_swapsi_hard, atomic_exchangesi_hard, atomic_fetch_si_hard, atomic_fetch_nandsi_hard, atomic__fetchsi_hard, atomic_nand_fetchsi_hard): Add TARGET_ATOMIC_STRICT check. (atomic_compare_and_swap_hard, atomic_exchange_hard, atomic_fetch__hard, atomic_fetch_nand_hard, atomic__fetch_hard, atomic_nand_fetch_hard, atomic_test_and_set_hard): Use TARGET_ATOMIC_HARD_LLCS condition. (atomic_compare_and_swap_soft, atomic_exchange_soft, atomic_fetch__soft, atomic_fetch_nand_soft, atomic__fetch_soft, atomic_nand_fetch_soft, atomic_test_and_set_soft): Append _gusa to the insn names and use TARGET_ATOMIC_SOFT_GUSA as condition. (atomic_compare_and_swap_soft_tcb, atomic_exchange_soft_tcb, atomic_fetch__soft_tcb, atomic_fetch_nand_soft_tcb, atomic__fetch_soft_tcb, atomic_nand_fetch_soft_tcb, atomic_test_and_set_soft_tcb): New insns. (atomic_compare_and_swap_soft_imask, atomic_exchange_soft_imask, atomic_fetch__soft_imask, atomic_fetch_nand_soft_imask, atomic__fetch_soft_imask, atomic_nand_fetch_soft_imask, atomic_test_and_set_soft_imask): New insns. * doc/invoke.texi (SH Options): Document new matomic-model option. Remove msoft-atomic and mhard-atomic options. Index: gcc/config/sh/sh.opt =================================================================== --- gcc/config/sh/sh.opt (revision 191865) +++ gcc/config/sh/sh.opt (working copy) @@ -320,12 +320,12 @@ Follow Renesas (formerly Hitachi) / SuperH calling conventions msoft-atomic -Target Report Var(TARGET_SOFT_ATOMIC) -Use gUSA software atomic sequences +Target Undocumented Alias(matomic-model=, soft-gusa, none) +Deprecated. Use -matomic= instead to select the atomic model -mhard-atomic -Target Report Var(TARGET_HARD_ATOMIC) -Use hardware atomic sequences +matomic-model= +Target Report RejectNegative Joined Var(sh_atomic_model_str) +Specify the model for atomic operations mtas Target Report RejectNegative Var(TARGET_ENABLE_TAS) Index: gcc/config/sh/predicates.md =================================================================== --- gcc/config/sh/predicates.md (revision 191865) +++ gcc/config/sh/predicates.md (working copy) @@ -1071,3 +1071,19 @@ return false; }) + +;; A predicate that determines whether a given constant is a valid +;; displacement for a gbr load/store of the specified mode. +(define_predicate "gbr_displacement" + (match_code "const_int") +{ + const int mode_sz = GET_MODE_SIZE (mode); + const int move_sz = mode_sz > GET_MODE_SIZE (SImode) + ? GET_MODE_SIZE (SImode) + : mode_sz; + int max_disp = 255 * move_sz; + if (mode_sz > move_sz) + max_disp -= mode_sz - move_sz; + + return INTVAL (op) >= 0 && INTVAL (op) <= max_disp; +}) Index: gcc/config/sh/sh-protos.h =================================================================== --- gcc/config/sh/sh-protos.h (revision 191865) +++ gcc/config/sh/sh-protos.h (working copy) @@ -37,6 +37,51 @@ SFUNC_STATIC }; +/* Atomic model. */ +struct sh_atomic_model +{ + enum enum_type + { + none = 0, + soft_gusa, + hard_llcs, + soft_tcb, + soft_imask, + + num_models + }; + + /* If strict is set, disallow mixing of different models, as it would + happen on SH4A. */ + bool strict; + enum_type type; + int tcb_gbr_offset; +}; + +extern const sh_atomic_model& selected_atomic_model (void); + +/* Shortcuts to check the currently selected atomic model. */ +#define TARGET_ATOMIC_ANY \ + selected_atomic_model ().type != sh_atomic_model::none + +#define TARGET_ATOMIC_STRICT \ + selected_atomic_model ().strict + +#define TARGET_ATOMIC_SOFT_GUSA \ + selected_atomic_model ().type == sh_atomic_model::soft_gusa + +#define TARGET_ATOMIC_HARD_LLCS \ + selected_atomic_model ().type == sh_atomic_model::hard_llcs + +#define TARGET_ATOMIC_SOFT_TCB \ + selected_atomic_model ().type == sh_atomic_model::soft_tcb + +#define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ + GEN_INT (selected_atomic_model ().tcb_gbr_offset) + +#define TARGET_ATOMIC_SOFT_IMASK \ + selected_atomic_model ().type == sh_atomic_model::soft_imask + #ifdef RTX_CODE extern rtx sh_fsca_sf2int (void); extern rtx sh_fsca_int2sf (void); Index: gcc/config/sh/linux.h =================================================================== --- gcc/config/sh/linux.h (revision 191865) +++ gcc/config/sh/linux.h (working copy) @@ -138,11 +138,16 @@ #define TARGET_INIT_LIBFUNCS sh_init_sync_libfuncs #undef SUBTARGET_OVERRIDE_OPTIONS -#define SUBTARGET_OVERRIDE_OPTIONS \ - do \ - { \ - /* Defaulting to -msoft-atomic. */ \ - if (global_options_set.x_TARGET_SOFT_ATOMIC == 0) \ - TARGET_SOFT_ATOMIC = 1; \ - } \ +#define SUBTARGET_OVERRIDE_OPTIONS \ + do \ + { \ + /* Set default atomic model if it hasn't been specified. */ \ + if (global_options_set.x_sh_atomic_model_str == 0) \ + { \ + if (TARGET_SH3) \ + sh_atomic_model_str = "soft-gusa"; \ + else if (TARGET_SH1) \ + sh_atomic_model_str = "soft-imask"; \ + } \ + } \ while (0) Index: gcc/config/sh/sh.c =================================================================== --- gcc/config/sh/sh.c (revision 191865) +++ gcc/config/sh/sh.c (working copy) @@ -62,6 +62,8 @@ #include "tm-constrs.h" #include "opts.h" +#include +#include #include int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; @@ -596,6 +598,110 @@ struct gcc_target targetm = TARGET_INITIALIZER; + +/* Information on the currently selected atomic model. + This is initialized in sh_option_override. */ +static sh_atomic_model selected_atomic_model_; + +const sh_atomic_model& +selected_atomic_model (void) +{ + return selected_atomic_model_; +} + +static sh_atomic_model +parse_validate_atomic_model_option (const char* str) +{ + const char* model_names[sh_atomic_model::num_models]; + model_names[sh_atomic_model::none] = "none"; + model_names[sh_atomic_model::soft_gusa] = "soft-gusa"; + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; + ret.strict = false; + ret.tcb_gbr_offset = -1; + + /* Handle empty string as 'none'. */ + if (str == NULL || *str == '\0') + return ret; + +#define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0) + + std::vector tokens; + for (std::stringstream ss (str); ss.good (); ) + { + tokens.push_back (std::string ()); + std::getline (ss, tokens.back (), ','); + } + + if (tokens.empty ()) + err_ret ("invalid atomic model option"); + + /* The first token must be the atomic model name. */ + { + for (size_t i = 0; i < sh_atomic_model::num_models; ++i) + if (tokens.front () == model_names[i]) + { + ret.type = (sh_atomic_model::enum_type)i; + goto got_mode_name; + } + + err_ret ("invalid atomic model name \"%s\"", tokens.front ().c_str ()); +got_mode_name:; + } + + /* Go through the remaining tokens. */ + for (size_t i = 1; i < tokens.size (); ++i) + { + if (tokens[i] == "strict") + ret.strict = true; + else if (tokens[i].find ("gbr-offset=") == 0) + { + std::string offset_str = tokens[i].substr (strlen ("gbr-offset=")); + ret.tcb_gbr_offset = integral_argument (offset_str.c_str ()); + if (offset_str.empty () || ret.tcb_gbr_offset == -1) + err_ret ("could not parse gbr-offset value \"%s\" in atomic model " + "option", offset_str.c_str ()); + } + else + err_ret ("unknown parameter \"%s\" in atomic model option", + tokens[i].c_str ()); + } + + /* Check that the selection makes sense. */ + if (TARGET_SHMEDIA && ret.type != sh_atomic_model::none) + err_ret ("atomic operations are not supported on SHmedia"); + + if (ret.type == sh_atomic_model::soft_gusa && !TARGET_SH3) + err_ret ("atomic model %s is only available on SH3 and SH4 targets", + model_names[ret.type]); + + if (ret.type == sh_atomic_model::hard_llcs && !TARGET_SH4A) + err_ret ("atomic model %s is only available on SH4A targets", + model_names[ret.type]); + + if (ret.type == sh_atomic_model::soft_tcb && ret.tcb_gbr_offset == -1) + err_ret ("atomic model %s requires gbr-offset parameter", + model_names[ret.type]); + + if (ret.type == sh_atomic_model::soft_tcb + && (ret.tcb_gbr_offset < 0 || ret.tcb_gbr_offset > 1020 + || (ret.tcb_gbr_offset & 3) != 0)) + err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be " + "a multiple of 4 in the range 0-1020", ret.tcb_gbr_offset, + model_names[ret.type]); + + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", model_names[ret.type]); + + return ret; + +#undef err_ret +} + /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override various options, and do some machine dependent initialization. */ static void @@ -907,12 +1013,10 @@ if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) flag_strict_volatile_bitfields = 1; - /* Make sure that only one atomic mode is selected and that the selection - is valid for the current target CPU. */ - if (TARGET_SOFT_ATOMIC && TARGET_HARD_ATOMIC) - error ("-msoft-atomic and -mhard-atomic cannot be used at the same time"); - if (TARGET_HARD_ATOMIC && ! TARGET_SH4A_ARCH) - error ("-mhard-atomic is only available for SH4A targets"); + /* Parse atomic model option and make sure it is valid for the current + target CPU. */ + selected_atomic_model_ + = parse_validate_atomic_model_option (sh_atomic_model_str); } /* Print the operand address in x to the stream. */ Index: gcc/config/sh/sh.h =================================================================== --- gcc/config/sh/sh.h (revision 191865) +++ gcc/config/sh/sh.h (working copy) @@ -172,9 +172,6 @@ (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \ && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) -/* Nonzero if either soft or hard atomics are enabled. */ -#define TARGET_ANY_ATOMIC (TARGET_SOFT_ATOMIC | TARGET_HARD_ATOMIC) - #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT SELECT_SH1 #define SUPPORT_SH1 1 @@ -436,20 +433,8 @@ "%{m2a*:%eSH2a does not support little-endian}}" #endif -#define UNSUPPORTED_ATOMIC_OPTIONS \ -"%{msoft-atomic:%{mhard-atomic:%e-msoft-atomic and -mhard-atomic cannot be \ -used at the same time}}" - -#if TARGET_CPU_DEFAULT & MASK_SH4A -#define UNSUPPORTED_HARD_ATOMIC_CPU "" -#else -#define UNSUPPORTED_HARD_ATOMIC_CPU \ -"%{!m4a*:%{mhard-atomic:%e-mhard-atomic is only available for SH4A targets}}" -#endif - #undef DRIVER_SELF_SPECS -#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A, UNSUPPORTED_ATOMIC_OPTIONS,\ - UNSUPPORTED_HARD_ATOMIC_CPU +#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A #define ASSEMBLER_DIALECT assembler_dialect Index: gcc/config/sh/sync.md =================================================================== --- gcc/config/sh/sync.md (revision 191865) +++ gcc/config/sh/sync.md (working copy) @@ -22,9 +22,12 @@ ;; Atomic integer operations for the Renesas / SuperH SH CPUs. ;; ;; On SH CPUs atomic integer operations can be done either in 'software' or -;; in 'hardware', where true hardware support was introduced with the SH4A. -;; In addition to that all SH CPUs support the 'tas.b' instruction, which -;; can be optionally used to implement the 'atomic_test_and_set' builtin. +;; in 'hardware' in various styles. True hardware support was introduced +;; with the SH4A. Some SH2A dual-core models (e.g. SH7205) also come with +;; 'semaphore' hardware registers, but these are currently unsupported. +;; All SH CPUs support the 'tas.b' instruction, which can be optionally used +;; to implement the 'atomic_test_and_set' builtin. +;; The following atomic options and models are supported. ;; ;; tas.b atomic_test_and_set (-mtas) ;; @@ -37,7 +40,7 @@ ;; other atomic operations. ;; ;; -;; Hardware Atomics (-mhard-atomic, SH4A only) +;; Hardware Atomics (-matomic-model=hard-llcs; SH4A only) ;; ;; Hardware atomics implement all atomic operations using the 'movli.l' and ;; 'movco.l' instructions that are availble on SH4A. On multi-core hardware @@ -48,7 +51,7 @@ ;; larger code. ;; ;; -;; Software Atomics (-msoft-atomic) +;; gUSA Software Atomics (-matomic-model=soft-gusa; SH3*, SH4* only) ;; ;; On single-core systems there can only be one execution context running ;; at a given point in time. This allows the usage of rewindable atomic @@ -68,9 +71,8 @@ ;; interrupted_pc = atomic_entrypoint; ;; ;; This method is also known as gUSA ("g" User Space Atomicity) and the -;; Linux kernel for SH3/SH4 implements support for such software -;; atomic sequences. However, it can also be implemented in freestanding -;; environments. +;; Linux kernel for SH3/SH4 implements support for such software atomic +;; sequences. It can also be implemented in freestanding environments. ;; ;; For this the following atomic sequence ABI is used. ;; @@ -111,16 +113,72 @@ ;; For correct operation the atomic sequences must not be rewound after ;; they have passed the write-back instruction. ;; +;; This is model works only on SH3* and SH4* because the stack pointer (r15) +;; is set to an invalid pointer temporarily. SH1* and SH2* CPUs will try +;; to push SR and PC registers on the stack when an interrupt / exception +;; occurs, and thus require the stack pointer (r15) always to be valid. +;; +;; +;; TCB Software Atomics (-matomic-model=soft-tcb) +;; +;; This model is a variation of the gUSA model. The concept of rewindable +;; atomic sequences is the same, but it does not use the stack pointer (r15) +;; for signaling the 'is in atomic sequence' condition. Instead, a variable +;; in the thread control block (TCB) is set to hold the exit point of the +;; atomic sequence. This assumes that the GBR is used as a thread pointer +;; register. The offset of the variable in the TCB to be used must be +;; specified with an additional option 'gbr-offset', such as: +;; -matomic-model=soft-tcb,gbr-offset=4 +;; +;; For this model the following atomic sequence ABI is used. +;; +;; @(#x,gbr) == 0: Execution context is not in an atomic sequence. +;; +;; @(#x,gbr) != 0: Execution context is in an atomic sequence. In this +;; case the following applies: +;; +;; @(#x,gbr): PC of the first instruction after the atomic +;; write-back instruction (exit point). +;; +;; r1: Negative byte length of the atomic sequence. +;; The entry point PC of the sequence can be +;; determined by doing @(#x,gbr) + r1 +;; +;; Note: #x is the user specified gbr-offset. +;; +;; +;; Interrupt-Flipping Software Atomics (-matomic-model=soft-imask) +;; +;; This model achieves atomicity by temporarily disabling interrupts for +;; the duration of the atomic sequence. This works only when the program +;; runs in privileged mode but does not require any support from the +;; interrupt / exception handling code. There is no particular ABI. +;; To disable interrupts the SR.IMASK bits are set to '1111'. +;; This method is not as efficient as the other software atomic models, +;; since loading and storing SR (in order to flip interrupts on / off) +;; requires using multi-cycle instructions. Moreover, it can potentially +;; increase the interrupt latency which might be important for hard-realtime +;; applications. +;; +;; +;; Compatibility Notes +;; +;; On single-core SH4A CPUs software atomic aware interrupt / exception code +;; is actually compatible with user code that utilizes hardware atomics. +;; Since SImode hardware atomic sequences are more compact on SH4A they are +;; always used, regardless of the selected atomic model. This atomic model +;; mixing can be disabled by setting the 'strict' flag, like: +;; -matomic-model=soft-gusa,strict +;; +;; The software atomic models are generally compatible with each other, +;; but the interrupt / exception handling code has to support both gUSA and +;; TCB models. +;; ;; The current atomic support is limited to QImode, HImode and SImode ;; atomic operations. DImode operations could also be implemented but ;; would require some ABI modifications to support multiple-instruction ;; write-back. This is because SH1/SH2/SH3/SH4 does not have a DImode ;; store instruction. DImode stores must be split into two SImode stores. -;; -;; On single-core SH4A CPUs software atomic aware interrupt / exception code -;; is actually compatible with user code that utilizes hardware atomics. -;; Since SImode hardware atomic sequences are more compact on SH4A they are -;; always used, regardless of the selected atomic mode. (define_c_enum "unspec" [ UNSPEC_ATOMIC @@ -158,7 +216,7 @@ (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; success model (match_operand:SI 7 "const_int_operand" "")] ;; failure model - "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY" { rtx addr = force_reg (Pmode, XEXP (operands[2], 0)); rtx old_val = gen_lowpart (SImode, operands[1]); @@ -166,12 +224,22 @@ rtx new_val = operands[4]; rtx atomic_insn; - if (TARGET_HARD_ATOMIC || (TARGET_SH4A_ARCH && mode == SImode)) + if (TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && mode == SImode && !TARGET_ATOMIC_STRICT)) atomic_insn = gen_atomic_compare_and_swap_hard (old_val, addr, exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, addr, + exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_TCB) + atomic_insn = gen_atomic_compare_and_swap_soft_tcb (old_val, addr, + exp_val, new_val, TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX); + else if (TARGET_ATOMIC_SOFT_IMASK) + atomic_insn = gen_atomic_compare_and_swap_soft_imask (old_val, addr, + exp_val, new_val); else - atomic_insn = gen_atomic_compare_and_swap_soft (old_val, addr, - exp_val, new_val); + FAIL; + emit_insn (atomic_insn); if (mode == QImode) @@ -196,7 +264,8 @@ (set (reg:SI T_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3)) (clobber (reg:SI R0_REG))] - "TARGET_ANY_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { return "\r0: movli.l @%1,r0" "\n" " cmp/eq %2,r0" "\n" @@ -224,7 +293,7 @@ (clobber (match_scratch:SI 4 "=&r")) (clobber (match_scratch:SI 5 "=&r")) (clobber (match_scratch:SI 6 "=1"))] - "TARGET_HARD_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS" { return "\r mov #-4,%5" "\n" " %2,%4" "\n" @@ -245,7 +314,7 @@ } [(set_attr "length" "30")]) -(define_insn "atomic_compare_and_swap_soft" +(define_insn "atomic_compare_and_swap_soft_gusa" [(set (match_operand:SI 0 "register_operand" "=&u") (unspec_volatile:SI [(mem:QIHISI (match_operand:SI 1 "register_operand" "u")) @@ -259,7 +328,7 @@ (clobber (match_scratch:SI 4 "=&u")) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA" { return "\r mova 1f,r0" "\n" " %2,%4" "\n" @@ -274,6 +343,86 @@ } [(set_attr "length" "20")]) +(define_insn "atomic_compare_and_swap_soft_tcb" + [(set (match_operand:SI 0 "register_operand" "=&r") + (unspec_volatile:SI + [(mem:QIHISI (match_operand:SI 1 "register_operand" "r")) + (match_operand:QIHISI 2 "register_operand" "r") + (match_operand:QIHISI 3 "register_operand" "r")] + UNSPECV_CMPXCHG_1)) + (set (mem:QIHISI (match_dup 1)) + (unspec_volatile:QIHISI [(const_int 0)] UNSPECV_CMPXCHG_2)) + (set (reg:SI T_REG) + (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3)) + (use (match_operand:SI 4 "gbr_displacement")) + (clobber (match_scratch:SI 5 "=&r")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_ATOMIC_SOFT_TCB" +{ + return "\r mova 1f,r0" "\n" + " .align 2" "\n" + " %2,%5" "\n" + " mov #(0f-1f),r1" "\n" + " mov.l r0,@(%O4,gbr)" "\n" + "0: mov. @%1,%0" "\n" + " mov #0,r0" "\n" + " cmp/eq %0,%5" "\n" + " bf 1f" "\n" + " mov. %3,@%1" "\n" + "1: mov.l r0,@(%O4,gbr)"; +} + [(set_attr "length" "22")]) + +(define_insn "atomic_compare_and_swap_soft_imask" + [(set (match_operand:SI 0 "register_operand" "=&z") + (unspec_volatile:SI + [(mem:QIHISI (match_operand:SI 1 "register_operand" "r")) + (match_operand:QIHISI 2 "register_operand" "r") + (match_operand:QIHISI 3 "register_operand" "r")] + UNSPECV_CMPXCHG_1)) + (set (mem:QIHISI (match_dup 1)) + (unspec_volatile:QIHISI [(const_int 0)] UNSPECV_CMPXCHG_2)) + (set (reg:SI T_REG) + (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3)) + (clobber (match_scratch:SI 4 "=&r")) + (clobber (match_scratch:SI 5 "=&r"))] + "TARGET_ATOMIC_SOFT_IMASK" +{ + /* The comparison result is supposed to be in T_REG. + Notice that restoring SR will overwrite the T_REG. We handle this by + rotating the T_REG into the saved SR before restoring SR. On SH2A we + can do one insn shorter by using the bst insn. */ + if (!TARGET_SH2A) + return "\r stc sr,%0" "\n" + " %2,%4" "\n" + " mov %0,%5" "\n" + " or #0xF0,%0" "\n" + " shlr %5" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " cmp/eq %4,%0" "\n" + " bf 1f" "\n" + " mov. %3,@%1" "\n" + "1: rotcl %5" "\n" + " ldc %5,sr"; + else + return "\r stc sr,%0" "\n" + " %2,%4" "\n" + " mov %0,%5" "\n" + " or #0xF0,%0" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " cmp/eq %4,%0" "\n" + " bst #0,%5" "\n" + " bf 1f" "\n" + " mov. %3,@%1" "\n" + "1: ldc %5,sr"; +} + [(set (attr "length") (if_then_else (match_test "!TARGET_SH2A") + (const_string "24") + (const_string "22")))]) + ;;------------------------------------------------------------------------------ ;; read - write - return old value @@ -282,16 +431,24 @@ (match_operand:QIHISI 1 "memory_operand" "") ;; memory (match_operand:QIHISI 2 "atomic_arith_operand" "") ;; newval input (match_operand:SI 3 "const_int_operand" "")] ;; memory model - "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); rtx val = operands[2]; rtx atomic_insn; - if (TARGET_HARD_ATOMIC || (TARGET_SH4A_ARCH && mode == SImode)) + if (TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && mode == SImode && !TARGET_ATOMIC_STRICT)) atomic_insn = gen_atomic_exchange_hard (operands[0], addr, val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_exchange_soft_gusa (operands[0], addr, val); + else if (TARGET_ATOMIC_SOFT_TCB) + atomic_insn = gen_atomic_exchange_soft_tcb (operands[0], addr, val, + TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX); + else if (TARGET_ATOMIC_SOFT_IMASK) + atomic_insn = gen_atomic_exchange_soft_imask (operands[0], addr, val); else - atomic_insn = gen_atomic_exchange_soft (operands[0], addr, val); + FAIL; emit_insn (atomic_insn); @@ -311,7 +468,8 @@ (unspec:SI [(match_operand:SI 2 "arith_operand" "rI08")] UNSPEC_ATOMIC)) (clobber (reg:SI R0_REG))] - "TARGET_ANY_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { return "\r0: movli.l @%1,r0" "\n" " mov r0,%0" "\n" @@ -330,7 +488,7 @@ (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] - "TARGET_HARD_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS" { return "\r mov #-4,%3" "\n" " and %1,%3" "\n" @@ -347,7 +505,7 @@ } [(set_attr "length" "24")]) -(define_insn "atomic_exchange_soft" +(define_insn "atomic_exchange_soft_gusa" [(set (match_operand:QIHISI 0 "register_operand" "=&u") (mem:QIHISI (match_operand:SI 1 "register_operand" "u"))) (set (mem:QIHISI (match_dup 1)) @@ -355,7 +513,7 @@ [(match_operand:QIHISI 2 "register_operand" "u")] UNSPEC_ATOMIC)) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA" { return "\r mova 1f,r0" "\n" " .align 2" "\n" @@ -367,6 +525,47 @@ } [(set_attr "length" "14")]) +(define_insn "atomic_exchange_soft_tcb" + [(set (match_operand:QIHISI 0 "register_operand" "=&r") + (mem:QIHISI (match_operand:SI 1 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(match_operand:QIHISI 2 "register_operand" "r")] UNSPEC_ATOMIC)) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG)) + (use (match_operand:SI 3 "gbr_displacement"))] + "TARGET_ATOMIC_SOFT_TCB" +{ + return "\r mova 1f,r0" "\n" + " mov #(0f-1f),r1" "\n" + " .align 2" "\n" + " mov.l r0,@(%O3,gbr)" "\n" + "0: mov. @%1,%0" "\n" + " mov #0,r0" "\n" + " mov. %2,@%1" "\n" + "1: mov.l r0,@(%O3,gbr)"; +} + [(set_attr "length" "16")]) + +(define_insn "atomic_exchange_soft_imask" + [(set (match_operand:QIHISI 0 "register_operand" "=&z") + (mem:QIHISI (match_operand:SI 1 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(match_operand:QIHISI 2 "register_operand" "r")] UNSPEC_ATOMIC)) + (clobber (match_scratch:SI 3 "=&r"))] + "TARGET_ATOMIC_SOFT_IMASK" +{ + return "\r stc sr,%0" "\n" + " mov %0,%3" "\n" + " or #0xF0,%0" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " mov. %2,@%1" "\n" + " ldc %3,sr"; +} + [(set_attr "length" "14")]) + ;;------------------------------------------------------------------------------ ;; read - add|sub|or|and|xor|nand - write - return old value @@ -379,18 +578,27 @@ (match_operand:QIHISI 2 "" ""))] UNSPEC_ATOMIC)) (match_operand:SI 3 "const_int_operand" "")] - "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); rtx atomic_insn; - if (TARGET_HARD_ATOMIC || (TARGET_SH4A_ARCH && mode == SImode)) + if (TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && mode == SImode && !TARGET_ATOMIC_STRICT)) atomic_insn = gen_atomic_fetch__hard (operands[0], addr, operands[2]); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_fetch__soft_gusa (operands[0], + addr, operands[2]); + else if (TARGET_ATOMIC_SOFT_TCB) + atomic_insn = gen_atomic_fetch__soft_tcb (operands[0], + addr, operands[2], TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX); + else if (TARGET_ATOMIC_SOFT_IMASK) + atomic_insn = gen_atomic_fetch__soft_imask (operands[0], + addr, operands[2]); else - atomic_insn = gen_atomic_fetch__soft (operands[0], - addr, - operands[2]); + FAIL; + emit_insn (atomic_insn); if (mode == QImode) @@ -411,7 +619,8 @@ (match_operand:SI 2 "" ""))] UNSPEC_ATOMIC)) (clobber (reg:SI R0_REG))] - "TARGET_ANY_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { return "\r0: movli.l @%1,r0" "\n" " mov r0,%0" "\n" @@ -432,7 +641,7 @@ (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] - "TARGET_HARD_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS" { return "\r mov #-4,%3" "\n" " and %1,%3" "\n" @@ -451,7 +660,7 @@ } [(set_attr "length" "28")]) -(define_insn "atomic_fetch__soft" +(define_insn "atomic_fetch__soft_gusa" [(set (match_operand:QIHISI 0 "register_operand" "=&u") (mem:QIHISI (match_operand:SI 1 "register_operand" "u"))) (set (mem:QIHISI (match_dup 1)) @@ -462,7 +671,7 @@ (clobber (match_scratch:QIHISI 3 "=&u")) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA" { return "\r mova 1f,r0" "\n" " .align 2" "\n" @@ -476,6 +685,57 @@ } [(set_attr "length" "18")]) +(define_insn "atomic_fetch__soft_tcb" + [(set (match_operand:QIHISI 0 "register_operand" "=&r") + (mem:QIHISI (match_operand:SI 1 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(FETCHOP:QIHISI (mem:QIHISI (match_dup 1)) + (match_operand:QIHISI 2 "register_operand" "r"))] + UNSPEC_ATOMIC)) + (use (match_operand:SI 3 "gbr_displacement")) + (clobber (match_scratch:QIHISI 4 "=&r")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_ATOMIC_SOFT_TCB" +{ + return "\r mova 1f,r0" "\n" + " mov #(0f-1f),r1" "\n" + " .align 2" "\n" + " mov.l r0,@(%O3,gbr)" "\n" + "0: mov. @%1,%0" "\n" + " mov #0,r0" "\n" + " mov %0,%4" "\n" + " %2,%4" "\n" + " mov. %4,@%1" "\n" + "1: mov.l r0,@(%O3,gbr)"; +} + [(set_attr "length" "20")]) + +(define_insn "atomic_fetch__soft_imask" + [(set (match_operand:QIHISI 0 "register_operand" "=&z") + (mem:QIHISI (match_operand:SI 1 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(FETCHOP:QIHISI (mem:QIHISI (match_dup 1)) + (match_operand:QIHISI 2 "register_operand" "r"))] + UNSPEC_ATOMIC)) + (clobber (match_scratch:QIHISI 3 "=&r")) + (clobber (match_scratch:SI 4 "=&r"))] + "TARGET_ATOMIC_SOFT_IMASK" +{ + return "\r stc sr,%0" "\n" + " mov %0,%4" "\n" + " or #0xF0,%0" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " mov %0,%3" "\n" + " %2,%3" "\n" + " mov. %3,@%1" "\n" + " ldc %4,sr"; +} + [(set_attr "length" "18")]) + (define_expand "atomic_fetch_nand" [(set (match_operand:QIHISI 0 "register_operand" "") (match_operand:QIHISI 1 "memory_operand" "")) @@ -485,17 +745,26 @@ (match_operand:QIHISI 2 "atomic_logical_operand" "")))] UNSPEC_ATOMIC)) (match_operand:SI 3 "const_int_operand" "")] - "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); rtx atomic_insn; - if (TARGET_HARD_ATOMIC || (TARGET_SH4A_ARCH && mode == SImode)) + if (TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && mode == SImode && !TARGET_ATOMIC_STRICT)) atomic_insn = gen_atomic_fetch_nand_hard (operands[0], addr, operands[2]); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_fetch_nand_soft_gusa (operands[0], addr, + operands[2]); + else if (TARGET_ATOMIC_SOFT_TCB) + atomic_insn = gen_atomic_fetch_nand_soft_tcb (operands[0], addr, + operands[2], TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX); + else if (TARGET_ATOMIC_SOFT_IMASK) + atomic_insn = gen_atomic_fetch_nand_soft_imask (operands[0], addr, + operands[2]); else - atomic_insn = gen_atomic_fetch_nand_soft (operands[0], addr, - operands[2]); + FAIL; emit_insn (atomic_insn); @@ -517,7 +786,8 @@ (match_operand:SI 2 "logical_operand" "rK08")))] UNSPEC_ATOMIC)) (clobber (reg:SI R0_REG))] - "TARGET_ANY_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { return "\r0: movli.l @%1,r0" "\n" " mov r0,%0" "\n" @@ -539,7 +809,7 @@ (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] - "TARGET_HARD_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS" { return "\r mov #-4,%3" "\n" " and %1,%3" "\n" @@ -559,7 +829,7 @@ } [(set_attr "length" "30")]) -(define_insn "atomic_fetch_nand_soft" +(define_insn "atomic_fetch_nand_soft_gusa" [(set (match_operand:QIHISI 0 "register_operand" "=&u") (mem:QIHISI (match_operand:SI 1 "register_operand" "u"))) (set (mem:QIHISI (match_dup 1)) @@ -570,7 +840,7 @@ (clobber (match_scratch:QIHISI 3 "=&u")) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA" { return "\r mova 1f,r0" "\n" " mov r15,r1" "\n" @@ -585,6 +855,59 @@ } [(set_attr "length" "20")]) +(define_insn "atomic_fetch_nand_soft_tcb" + [(set (match_operand:QIHISI 0 "register_operand" "=&r") + (mem:QIHISI (match_operand:SI 1 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(not:QIHISI (and:QIHISI (mem:QIHISI (match_dup 1)) + (match_operand:QIHISI 2 "register_operand" "r")))] + UNSPEC_ATOMIC)) + (use (match_operand:SI 3 "gbr_displacement")) + (clobber (match_scratch:QIHISI 4 "=&r")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_ATOMIC_SOFT_TCB" +{ + return "\r mova 1f,r0" "\n" + " .align 2" "\n" + " mov #(0f-1f),r1" "\n" + " mov.l r0,@(%O3,gbr)" "\n" + "0: mov. @%1,%0" "\n" + " mov #0,r0" "\n" + " mov %2,%4" "\n" + " and %0,%4" "\n" + " not %4,%4" "\n" + " mov. %4,@%1" "\n" + "1: mov.l r0,@(%O3,gbr)"; +} + [(set_attr "length" "22")]) + +(define_insn "atomic_fetch_nand_soft_imask" + [(set (match_operand:QIHISI 0 "register_operand" "=&z") + (mem:QIHISI (match_operand:SI 1 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(not:QIHISI (and:QIHISI (mem:QIHISI (match_dup 1)) + (match_operand:QIHISI 2 "register_operand" "r")))] + UNSPEC_ATOMIC)) + (clobber (match_scratch:QIHISI 3 "=&r")) + (clobber (match_scratch:SI 4 "=&r"))] + "TARGET_ATOMIC_SOFT_IMASK" +{ + return "\r stc sr,%0" "\n" + " mov %0,%4" "\n" + " or #0xF0,%0" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " mov %2,%3" "\n" + " and %0,%3" "\n" + " not %3,%3" "\n" + " mov. %3,@%1" "\n" + " stc %4,sr"; +} + [(set_attr "length" "20")]) + ;;------------------------------------------------------------------------------ ;; read - add|sub|or|and|xor|nand - write - return new value @@ -598,17 +921,27 @@ [(FETCHOP:QIHISI (match_dup 1) (match_dup 2))] UNSPEC_ATOMIC)) (match_operand:SI 3 "const_int_operand" "")] - "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); rtx atomic_insn; - if (TARGET_HARD_ATOMIC || (TARGET_SH4A_ARCH && mode == SImode)) + if (TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && mode == SImode && !TARGET_ATOMIC_STRICT)) atomic_insn = gen_atomic__fetch_hard (operands[0], addr, operands[2]); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic__fetch_soft_gusa (operands[0], + addr, operands[2]); + else if (TARGET_ATOMIC_SOFT_TCB) + atomic_insn = gen_atomic__fetch_soft_tcb (operands[0], + addr, operands[2], TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX); + else if (TARGET_ATOMIC_SOFT_IMASK) + atomic_insn = gen_atomic__fetch_soft_imask (operands[0], + addr, operands[2]); else - atomic_insn = gen_atomic__fetch_soft (operands[0], addr, - operands[2]); + FAIL; + emit_insn (atomic_insn); if (mode == QImode) @@ -629,7 +962,8 @@ (unspec:SI [(FETCHOP:SI (mem:SI (match_dup 1)) (match_dup 2))] UNSPEC_ATOMIC))] - "TARGET_ANY_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { return "\r0: movli.l @%1,%0" "\n" " %2,%0" "\n" @@ -647,11 +981,10 @@ (unspec:QIHI [(FETCHOP:QIHI (mem:QIHI (match_dup 1)) (match_dup 2))] UNSPEC_ATOMIC)) - (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] - "TARGET_HARD_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS" { return "\r mov #-4,%3" "\n" " and %1,%3" "\n" @@ -670,7 +1003,7 @@ } [(set_attr "length" "28")]) -(define_insn "atomic__fetch_soft" +(define_insn "atomic__fetch_soft_gusa" [(set (match_operand:QIHISI 0 "register_operand" "=&u") (FETCHOP:QIHISI (mem:QIHISI (match_operand:SI 1 "register_operand" "u")) @@ -681,7 +1014,7 @@ UNSPEC_ATOMIC)) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA" { return "\r mova 1f,r0" "\n" " mov r15,r1" "\n" @@ -694,6 +1027,55 @@ } [(set_attr "length" "16")]) +(define_insn "atomic__fetch_soft_tcb" + [(set (match_operand:QIHISI 0 "register_operand" "=&r") + (FETCHOP:QIHISI + (mem:QIHISI (match_operand:SI 1 "register_operand" "r")) + (match_operand:QIHISI 2 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(FETCHOP:QIHISI (mem:QIHISI (match_dup 1)) (match_dup 2))] + UNSPEC_ATOMIC)) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG)) + (use (match_operand:SI 3 "gbr_displacement"))] + "TARGET_ATOMIC_SOFT_TCB" +{ + return "\r mova 1f,r0" "\n" + " .align 2" "\n" + " mov #(0f-1f),r1" "\n" + " mov.l r0,@(%O3,gbr)" "\n" + "0: mov. @%1,%0" "\n" + " mov #0,r0" "\n" + " %2,%0" "\n" + " mov. %0,@%1" "\n" + "1: mov.l r0,@(%O3,gbr)"; +} + [(set_attr "length" "18")]) + +(define_insn "atomic__fetch_soft_imask" + [(set (match_operand:QIHISI 0 "register_operand" "=&z") + (FETCHOP:QIHISI + (mem:QIHISI (match_operand:SI 1 "register_operand" "r")) + (match_operand:QIHISI 2 "register_operand" "r"))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(FETCHOP:QIHISI (mem:QIHISI (match_dup 1)) (match_dup 2))] + UNSPEC_ATOMIC)) + (clobber (match_scratch:SI 3 "=&r"))] + "TARGET_ATOMIC_SOFT_IMASK" +{ + return "\r stc sr,%0" "\n" + " mov %0,%3" "\n" + " or #0xF0,%0" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " %2,%0" "\n" + " mov. %0,@%1" "\n" + " ldc %3,sr"; +} + [(set_attr "length" "16")]) + (define_expand "atomic_nand_fetch" [(set (match_operand:QIHISI 0 "register_operand" "") (not:QIHISI (and:QIHISI @@ -704,17 +1086,27 @@ [(not:QIHISI (and:QIHISI (match_dup 1) (match_dup 2)))] UNSPEC_ATOMIC)) (match_operand:SI 3 "const_int_operand" "")] - "TARGET_ANY_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); rtx atomic_insn; - if (TARGET_HARD_ATOMIC || (TARGET_SH4A_ARCH && mode == SImode)) + if (TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && mode == SImode && !TARGET_ATOMIC_STRICT)) atomic_insn = gen_atomic_nand_fetch_hard (operands[0], addr, operands[2]); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_nand_fetch_soft_gusa (operands[0], addr, + operands[2]); + else if (TARGET_ATOMIC_SOFT_TCB) + atomic_insn = gen_atomic_nand_fetch_soft_tcb (operands[0], addr, + operands[2], TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX); + else if (TARGET_ATOMIC_SOFT_IMASK) + atomic_insn = gen_atomic_nand_fetch_soft_imask (operands[0], addr, + operands[2]); else - atomic_insn = gen_atomic_nand_fetch_soft (operands[0], addr, - operands[2]); + FAIL; + emit_insn (atomic_insn); if (mode == QImode) @@ -734,7 +1126,8 @@ (unspec:SI [(not:SI (and:SI (mem:SI (match_dup 1)) (match_dup 2)))] UNSPEC_ATOMIC))] - "TARGET_ANY_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS + || (TARGET_SH4A_ARCH && TARGET_ATOMIC_ANY && !TARGET_ATOMIC_STRICT)" { return "\r0: movli.l @%1,%0" "\n" " and %2,%0" "\n" @@ -756,7 +1149,7 @@ (clobber (reg:SI R0_REG)) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=1"))] - "TARGET_HARD_ATOMIC && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS" { return "\r mov #-4,%3" "\n" " and %1,%3" "\n" @@ -775,7 +1168,7 @@ } [(set_attr "length" "28")]) -(define_insn "atomic_nand_fetch_soft" +(define_insn "atomic_nand_fetch_soft_gusa" [(set (match_operand:QIHISI 0 "register_operand" "=&u") (not:QIHISI (and:QIHISI (mem:QIHISI (match_operand:SI 1 "register_operand" "u")) @@ -786,7 +1179,7 @@ UNSPEC_ATOMIC)) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA" { return "\r mova 1f,r0" "\n" " .align 2" "\n" @@ -800,6 +1193,57 @@ } [(set_attr "length" "18")]) +(define_insn "atomic_nand_fetch_soft_tcb" + [(set (match_operand:QIHISI 0 "register_operand" "=&r") + (not:QIHISI (and:QIHISI + (mem:QIHISI (match_operand:SI 1 "register_operand" "r")) + (match_operand:QIHISI 2 "register_operand" "r")))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(not:QIHISI (and:QIHISI (mem:QIHISI (match_dup 1)) (match_dup 2)))] + UNSPEC_ATOMIC)) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG)) + (use (match_operand:SI 3 "gbr_displacement"))] + "TARGET_ATOMIC_SOFT_TCB" +{ + return "\r mova 1f,r0" "\n" + " mov #(0f-1f),r1" "\n" + " .align 2" "\n" + " mov.l r0,@(%O3,gbr)" "\n" + "0: mov. @%1,%0" "\n" + " mov #0,r0" "\n" + " and %2,%0" "\n" + " not %0,%0" "\n" + " mov. %0,@%1" "\n" + "1: mov.l r0,@(%O3,gbr)"; +} + [(set_attr "length" "20")]) + +(define_insn "atomic_nand_fetch_soft_imask" + [(set (match_operand:QIHISI 0 "register_operand" "=&z") + (not:QIHISI (and:QIHISI + (mem:QIHISI (match_operand:SI 1 "register_operand" "r")) + (match_operand:QIHISI 2 "register_operand" "r")))) + (set (mem:QIHISI (match_dup 1)) + (unspec:QIHISI + [(not:QIHISI (and:QIHISI (mem:QIHISI (match_dup 1)) (match_dup 2)))] + UNSPEC_ATOMIC)) + (clobber (match_scratch:SI 3 "=&r"))] + "TARGET_ATOMIC_SOFT_IMASK" +{ + return "\r stc sr,%0" "\n" + " mov %0,%3" "\n" + " or #0xF0,%0" "\n" + " ldc %0,sr" "\n" + " mov. @%1,%0" "\n" + " and %2,%0" "\n" + " not %0,%0" "\n" + " mov. %0,@%1" "\n" + " ldc %3,sr"; +} + [(set_attr "length" "18")]) + ;;------------------------------------------------------------------------------ ;; read - test against zero - or with 0x80 - write - return test result @@ -807,7 +1251,7 @@ [(match_operand:SI 0 "register_operand" "") ;; bool result output (match_operand:QI 1 "memory_operand" "") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "(TARGET_ANY_ATOMIC || TARGET_ENABLE_TAS) && !TARGET_SHMEDIA" + "(TARGET_ATOMIC_ANY || TARGET_ENABLE_TAS) && !TARGET_SHMEDIA" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); @@ -818,10 +1262,17 @@ rtx val = gen_int_mode (targetm.atomic_test_and_set_trueval, QImode); val = force_reg (QImode, val); - if (TARGET_HARD_ATOMIC) + if (TARGET_ATOMIC_HARD_LLCS) emit_insn (gen_atomic_test_and_set_hard (addr, val)); + else if (TARGET_ATOMIC_SOFT_GUSA) + emit_insn (gen_atomic_test_and_set_soft_gusa (addr, val)); + else if (TARGET_ATOMIC_SOFT_TCB) + emit_insn (gen_atomic_test_and_set_soft_tcb (addr, val, + TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX)); + else if (TARGET_ATOMIC_SOFT_IMASK) + emit_insn (gen_atomic_test_and_set_soft_imask (addr, val)); else - emit_insn (gen_atomic_test_and_set_soft (addr, val)); + FAIL; } /* The result of the test op is the inverse of what we are @@ -841,7 +1292,7 @@ "tas.b @%0" [(set_attr "insn_class" "co_group")]) -(define_insn "atomic_test_and_set_soft" +(define_insn "atomic_test_and_set_soft_gusa" [(set (reg:SI T_REG) (eq:SI (mem:QI (match_operand:SI 0 "register_operand" "u")) (const_int 0))) @@ -850,7 +1301,7 @@ (clobber (match_scratch:QI 2 "=&u")) (clobber (reg:SI R0_REG)) (clobber (reg:SI R1_REG))] - "TARGET_SOFT_ATOMIC && !TARGET_ENABLE_TAS && !TARGET_SHMEDIA" + "TARGET_ATOMIC_SOFT_GUSA && !TARGET_ENABLE_TAS" { return "\r mova 1f,r0" "\n" " .align 2" "\n" @@ -863,6 +1314,51 @@ } [(set_attr "length" "16")]) +(define_insn "atomic_test_and_set_soft_tcb" + [(set (reg:SI T_REG) + (eq:SI (mem:QI (match_operand:SI 0 "register_operand" "r")) + (const_int 0))) + (set (mem:QI (match_dup 0)) + (unspec:QI [(match_operand:QI 1 "register_operand" "r")] UNSPEC_ATOMIC)) + (use (match_operand:SI 2 "gbr_displacement")) + (clobber (match_scratch:QI 3 "=&r")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_ATOMIC_SOFT_TCB && !TARGET_ENABLE_TAS" +{ + return "\r mova 1f,r0" "\n" + " mov #(0f-1f),r1" "\n" + " .align 2" "\n" + " mov.l r0,@(%O2,gbr)" "\n" + "0: mov.b @%0,%3" "\n" + " mov #0,r0" "\n" + " mov.b %1,@%0" "\n" + "1: mov.l r0,@(%O2,gbr)" "\n" + " tst %3,%3"; +} + [(set_attr "length" "18")]) + +(define_insn "atomic_test_and_set_soft_imask" + [(set (reg:SI T_REG) + (eq:SI (mem:QI (match_operand:SI 0 "register_operand" "r")) + (const_int 0))) + (set (mem:QI (match_dup 0)) + (unspec:QI [(match_operand:QI 1 "register_operand" "r")] UNSPEC_ATOMIC)) + (clobber (match_scratch:SI 2 "=&r")) + (clobber (reg:SI R0_REG))] + "TARGET_ATOMIC_SOFT_IMASK && !TARGET_ENABLE_TAS" +{ + return "\r stc sr,r0" "\n" + " mov r0,%2" "\n" + " or #0xF0,r0" "\n" + " ldc r0,sr" "\n" + " mov.b @%0,r0" "\n" + " mov.b %1,@%0" "\n" + " stc %2,sr" "\n" + " tst r0,r0"; +} + [(set_attr "length" "16")]) + (define_insn "atomic_test_and_set_hard" [(set (reg:SI T_REG) (eq:SI (mem:QI (match_operand:SI 0 "register_operand" "r")) @@ -873,7 +1369,7 @@ (clobber (match_scratch:SI 2 "=&r")) (clobber (match_scratch:SI 3 "=&r")) (clobber (match_scratch:SI 4 "=0"))] - "TARGET_HARD_ATOMIC && !TARGET_ENABLE_TAS && TARGET_SH4A_ARCH" + "TARGET_ATOMIC_HARD_LLCS && !TARGET_ENABLE_TAS" { return "\r mov #-4,%2" "\n" " and %0,%2" "\n" Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 191865) +++ gcc/doc/invoke.texi (working copy) @@ -891,7 +891,8 @@ -mspace -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol --maccumulate-outgoing-args -minvalid-symbols -msoft-atomic -mhard-atomic @gol +-maccumulate-outgoing-args -minvalid-symbols @gol +-matomic-model=@var{atomic-model} @gol -mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch -mcbranchdi -mcmpeqdi @gol -mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol -mpretend-cmove -mtas} @@ -18212,27 +18213,68 @@ This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI@. -@item -msoft-atomic -@opindex msoft-atomic +@item -matomic-model=@var{model} +@opindex matomic-model=@var{model} +Sets the model of atomic operations and additional parameters as a comma +separated list. For details on the atomic built-in functions see +@ref{__atomic Builtins}. The following models and parameters are supported: + +@table @samp + +@item none +Disable compiler generated atomic sequences and emit library calls for atomic +operations. This is the default if the target is not @code{sh-*-linux*}. + +@item soft-gusa Generate GNU/Linux compatible gUSA software atomic sequences for the atomic -built-in functions. The generated atomic sequences require support from the -interrupt / exception handling code of the system and are only suitable for -single-core systems. They will not operate correctly on multi-core systems. -This option is enabled by default when the target is @code{sh-*-linux*}. -When the target is SH4A, this option will also partially utilize the hardware -atomic instructions @code{movli.l} and @code{movco.l} to create more -efficient code. -For details on the atomic built-in functions see @ref{__atomic Builtins}. +built-in functions. The generated atomic sequences require additional support +from the interrupt/exception handling code of the system and are only suitable +for SH3* and SH4* single-core systems. This option is enabled by default when +the target is @code{sh-*-linux*} and SH3* or SH4*. When the target is SH4A, +this option will also partially utilize the hardware atomic instructions +@code{movli.l} and @code{movco.l} to create more efficient code, unless +@samp{strict} is specified. -@item -mhard-atomic -@opindex hard-atomic -Generate hardware atomic sequences for the atomic built-in functions. This -is only available on SH4A and is suitable for multi-core systems. Code -compiled with this option will also be compatible with gUSA aware -interrupt / exception handling systems. In contrast to the -@option{-msoft-atomic} option this will only use the instructions -@code{movli.l} and @code{movco.l} to create atomic sequences. +@item soft-tcb +Generate software atomic sequences that use a variable in the thread control +block. This is a variation of the gUSA sequences which can also be used on +SH1* and SH2* targets. The generated atomic sequences require additional +support from the interrupt/exception handling code of the system and are only +suitable for single-core systems. When using this model, the @samp{gbr-offset=} +parameter has to be specified as well. +@item soft-imask +Generate software atomic sequences that temporarily disable interrupts by +setting @code{SR.IMASK = 1111}. This model works only when the program runs +in privileged mode and is only suitable for single-core systems. Additional +support from the interrupt/exception handling code of the system is not +required. This model is enabled by default when the target is +@code{sh-*-linux*} and SH1* or SH2*. + +@item hard-llcs +Generate hardware atomic sequences using the @code{movli.l} and @code{movco.l} +instructions only. This is only available on SH4A and is suitable for +multi-core systems. Since the hardware instructions support only 32 bit atomic +variables access to 8 or 16 bit variables is emulated with 32 bit accesses. +Code compiled with this option will also be compatible with other software +atomic model interrupt/exception handling systems if executed on an SH4A +system. Additional support from the interrupt/exception handling code of the +system is not required for this model. + +@item gbr-offset= +This parameter specifies the offset in bytes of the variable in the thread +control block structure that should be used by the generated atomic sequences +when the @samp{soft-tcb} model has been selected. For other models this +parameter is ignored. The specified value must be an integer multiple of four +and in the range 0-1020. + +@item strict +This parameter prevents mixed usage of multiple atomic models, even though they +would be compatible, and will make the compiler generate atomic sequences of the +specified model only. + +@end table + @item -mtas @opindex mtas Generate the @code{tas.b} opcode for @code{__atomic_test_and_set}.