From patchwork Fri Sep 28 00:57:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D66F62C00A9 for ; Fri, 28 Sep 2012 10:57:24 +1000 (EST) Received: from localhost ([::1]:34706 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOtO-0007yq-VI for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 20:57:22 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOtI-0007ya-C0 for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:57:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THOtH-0006QD-4n for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:57:16 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:62523) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOtG-0006Q9-Ud for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:57:15 -0400 Received: by pbbrp2 with SMTP id rp2so4383935pbb.4 for ; Thu, 27 Sep 2012 17:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=YflCiYKjyhUFrJayPnX/EwKLH0QU0GZOjtzRu8FE1sE=; b=VDnKDlzA/n6AX77LoGiP2f99BPEUFx6ratbiqliysnLith5Rc3C3v+GXjW6KnPLICj bxhSwz8yJ7ih7Wfs6z4bBjHNg1E3a6lrqBwX9x51pyDmp9zXHZklVBFwiptPreG+GAol 1M0Z+1gLb8d8tn47IxTuFWuGOns6/CIkEeqoYRpextmempGszxSdPczEUppuOi0LVFni sJVUUWRuROkk866/0ffl0uBeN3tAsHsFcfcmu4EKbsBF6eUgIUak/AK1yZVEyZHm++wY jLbGosKawgCH+6pf1qny0Yg4rxYcYFnpAVgj8otw45lJMhUqteIqiZGaQ6jsspl7dNK3 FA5A== Received: by 10.66.89.37 with SMTP id bl5mr13639637pab.55.1348793834219; Thu, 27 Sep 2012 17:57:14 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id vu7sm339557pbc.9.2012.09.27.17.57.12 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 17:57:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 17:57:10 -0700 Message-Id: <1348793830-27910-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 121/147] target-s390: Implement RISBG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 5 +++ target-s390x/translate.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 4478d1c..c80a386 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -500,6 +500,11 @@ C(0xeb1d, RLL, RSY_a, Z, r3_o, sh32, new, r1_32, rll32, 0) C(0xeb1c, RLLG, RSY_a, Z, r3_o, sh64, r1, 0, rll64, 0) +/* ROTATE THEN INSERT SELECTED BITS */ + C(0xec55, RISBG, RIE_f, GIE, 0, r2, r1, 0, risbg, s64) + C(0xec5d, RISBHG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) + C(0xec51, RISBLG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) + /* SEARCH STRING */ C(0xb25e, SRST, RRE, Z, r1_o, r2_o, 0, 0, srst, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 1130902..3fa0213 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2429,6 +2429,89 @@ static ExitStatus op_ptlb(DisasContext *s, DisasOps *o) } #endif +static ExitStatus op_risbg(DisasContext *s, DisasOps *o) +{ + int i3 = get_field(s->fields, i3); + int i4 = get_field(s->fields, i4); + int i5 = get_field(s->fields, i5); + int do_zero = i4 & 0x80; + uint64_t mask, imask, pmask; + int pos, len, rot; + + /* Adjust the arguments for the specific insn. */ + switch (s->fields->op2) { + case 0x55: /* risbg */ + i3 &= 63; + i4 &= 63; + pmask = ~0; + break; + case 0x5d: /* risbhg */ + i3 &= 31; + i4 &= 31; + pmask = 0xffffffff00000000ull; + break; + case 0x51: /* risblg */ + i3 &= 31; + i4 &= 31; + pmask = 0x00000000ffffffffull; + break; + default: + abort(); + } + + /* MASK is the set of bits to be inserted from R2. + Take care for I3/I4 wraparound. */ + mask = pmask >> i3; + if (i3 <= i4) { + mask ^= pmask >> i4 >> 1; + } else { + mask |= ~(pmask >> i4 >> 1); + } + mask &= pmask; + + /* IMASK is the set of bits to be kept from R1. In the case of the high/low + insns, we need to keep the other half of the register. */ + imask = ~mask | ~pmask; + if (do_zero) { + if (s->fields->op2 == 0x55) { + imask = 0; + } else { + imask = ~pmask; + } + } + + /* In some cases we can implement this with deposit, which can be more + efficient on some hosts. */ + if (~mask == imask && i3 <= i4) { + if (s->fields->op2 == 0x5d) { + i3 += 32, i4 += 32; + } + /* Note that we rotate the bits to be inserted to the lsb, not to + the position as described in the PoO. */ + len = i4 - i3 + 1; + pos = 63 - i4; + rot = (i5 - pos) & 63; + } else { + pos = len = -1; + rot = i5 & 63; + } + + /* Rotate the input as necessary. */ + tcg_gen_rotli_i64(o->in2, o->in2, rot); + + /* Insert the selected bits into the output. */ + if (pos >= 0) { + tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len); + } else if (imask == 0) { + tcg_gen_andi_i64(o->out, o->in2, mask); + } else { + tcg_gen_andi_i64(o->in2, o->in2, mask); + tcg_gen_andi_i64(o->out, o->out, imask); + tcg_gen_or_i64(o->out, o->out, o->in2); + } + return NO_EXIT; +} + static ExitStatus op_rev16(DisasContext *s, DisasOps *o) { tcg_gen_bswap16_i64(o->out, o->in2);