From patchwork Fri Sep 28 00:23:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8A9F52C00A2 for ; Fri, 28 Sep 2012 10:23:27 +1000 (EST) Received: from localhost ([::1]:40604 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOMX-0002eU-J1 for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 20:23:25 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOMQ-0002eN-Oh for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:23:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THOMP-0003OI-Js for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:23:18 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:48859) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THOMP-0003OC-DI for qemu-devel@nongnu.org; Thu, 27 Sep 2012 20:23:17 -0400 Received: by pbbrp2 with SMTP id rp2so4353612pbb.4 for ; Thu, 27 Sep 2012 17:23:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=lPEnfkabLWo/OGfHDWwQQzQPEitzAQkjN0u/8qELnkI=; b=x9jEAN9D99AoKyJxoAdzM6bl9yiK5/twICH4QcnpNtH+zUXmuR86pmacfeKJjpYQnp gIYNv+dY6fC/u0T6YYXcFza36eOUK85JsdenjCASjyQ36mmL5g+bO74WOr3E0bBPauu3 JeSVV7avSBg2aOVm8hCb263xy3f2lQuiRONkS3ersXUBYq9iyrImcnwD74cQnz6W1NBV Kry2No/kNJrcON3Kk80h0dcfE7xBRw7XHyKe8oU2JzhxjHi08m1NPPbk/ItI98XXoptB /BYxdicb+QSRVI82GnLj3o2bIkAXIJauPPpx4s9n33vDU8Ie/exYD0iFMtZDZTo/mE6K 7MqA== Received: by 10.68.135.234 with SMTP id pv10mr15531524pbb.156.1348791796617; Thu, 27 Sep 2012 17:23:16 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id nz6sm4602160pbb.50.2012.09.27.17.23.15 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 17:23:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 17:23:13 -0700 Message-Id: <1348791793-26522-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 089/147] target-s390: Convert IPM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Note that the previous placement of the PM field was incorrect. Signed-off-by: Richard Henderson --- target-s390x/cc_helper.c | 12 ------------ target-s390x/helper.h | 1 - target-s390x/insn-data.def | 2 ++ target-s390x/translate.c | 25 +++++++++++++++++++------ 4 files changed, 21 insertions(+), 19 deletions(-) diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index 46c6d84..78c0cb2 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -544,18 +544,6 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src, return do_calc_cc(env, cc_op, src, dst, vr); } -/* insert psw mask and condition code into r1 */ -void HELPER(ipm)(CPUS390XState *env, uint32_t cc, uint32_t r1) -{ - uint64_t r = env->regs[r1]; - - r &= 0xffffffff00ffffffULL; - r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf); - env->regs[r1] = r; - HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__, - cc, env->psw.mask, r); -} - #ifndef CONFIG_USER_ONLY void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { diff --git a/target-s390x/helper.h b/target-s390x/helper.h index e8300ec..5ae723e 100644 --- a/target-s390x/helper.h +++ b/target-s390x/helper.h @@ -25,7 +25,6 @@ DEF_HELPER_FLAGS_1(abs_i32, TCG_CALL_PURE|TCG_CALL_CONST, i32, s32) DEF_HELPER_FLAGS_1(nabs_i32, TCG_CALL_PURE|TCG_CALL_CONST, s32, s32) DEF_HELPER_FLAGS_1(abs_i64, TCG_CALL_PURE|TCG_CALL_CONST, i64, s64) DEF_HELPER_FLAGS_1(nabs_i64, TCG_CALL_PURE|TCG_CALL_CONST, s64, s64) -DEF_HELPER_3(ipm, void, env, i32, i32) DEF_HELPER_4(stam, void, env, i32, i64, i32) DEF_HELPER_4(lam, void, env, i32, i64, i32) DEF_HELPER_4(mvcle, i32, env, i32, i64, i32) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index b319beb..13b1771 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -237,6 +237,8 @@ D(0xa501, IIHL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1020) D(0xa502, IILH, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1010) D(0xa503, IILL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1000) +/* INSERT PROGRAM MASK */ + C(0xb222, IPM, RRE, Z, 0, 0, r1, 0, ipm, 0) /* LOAD */ C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 9f8fcb5..4990e57 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1034,12 +1034,6 @@ static void disas_b2(CPUS390XState *env, DisasContext *s, int op, LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2); switch (op) { - case 0x22: /* IPM R1 [RRE] */ - tmp32_1 = tcg_const_i32(r1); - gen_op_calc_cc(s); - gen_helper_ipm(cpu_env, cc_op, tmp32_1); - tcg_temp_free_i32(tmp32_1); - break; case 0x41: /* CKSM R1,R2 [RRE] */ tmp32_1 = tcg_const_i32(r1); tmp32_2 = tcg_const_i32(r2); @@ -2348,6 +2342,25 @@ static ExitStatus op_insi(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_ipm(DisasContext *s, DisasOps *o) +{ + TCGv_i64 t1; + + gen_op_calc_cc(s); + tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull); + + t1 = tcg_temp_new_i64(); + tcg_gen_shli_i64(t1, psw_mask, 20); + tcg_gen_shri_i64(t1, t1, 36); + tcg_gen_or_i64(o->out, o->out, t1); + + tcg_gen_extu_i32_i64(t1, cc_op); + tcg_gen_shli_i64(t1, t1, 28); + tcg_gen_or_i64(o->out, o->out, t1); + tcg_temp_free_i64(t1); + return NO_EXIT; +} + static ExitStatus op_ldeb(DisasContext *s, DisasOps *o) { gen_helper_ldeb(o->out, cpu_env, o->in2);