From patchwork Thu Sep 27 23:34:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 420132C00B4 for ; Fri, 28 Sep 2012 09:34:29 +1000 (EST) Received: from localhost ([::1]:35622 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THNb9-0001gS-CW for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 19:34:27 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57719) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THNb1-0001fy-DV for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:34:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THNb0-0003To-3L for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:34:19 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:62420) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THNaz-0003Td-TZ for qemu-devel@nongnu.org; Thu, 27 Sep 2012 19:34:18 -0400 Received: by padfb10 with SMTP id fb10so1766197pad.4 for ; Thu, 27 Sep 2012 16:34:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Xia7cLXqsNZ0560f2gBedecnAqLxVQkwQcTVUGlDTmo=; b=gVphOD5SrMAwJHg0COUgN1ixdGWFaxy3+vqBqo/b+/goKAzj65PBn00C9fNmXRz5rh nU2/UjfgTgQ4LEk5qQKyUjDO3/eXigMyRegArBhk7w64sqSEC/LTwBNrfIZz6LVA/yHB Xg0YUfjvdGOUhCkHTNgLypw7FgBtQB38jKlkf6rf5/3iUP2wg7ZIVHnPCNpsV4iiWDHl GvDhWqmXCQmDke78B11q34Ox/QtDngVcYUa+nDe8IocAdqap2XecKI7WDjqg87b51FZy yyA+DT4SQC2LWbWpgkx2Y6ckWtIcdU7Z1PFCrjEXpKZYqBj7v/I5EqFNrWZOqMVUahmN XKHQ== Received: by 10.66.85.233 with SMTP id k9mr12915817paz.73.1348788857261; Thu, 27 Sep 2012 16:34:17 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id wl4sm4548938pbc.17.2012.09.27.16.34.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 16:34:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 16:34:13 -0700 Message-Id: <1348788853-24491-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 043/147] target-s390: Convert INSERT CHARACTER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 3 +++ target-s390x/translate.c | 35 +++++++++++++---------------------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index c3b1f6f..f37e69a 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -157,6 +157,9 @@ D(0xc006, XIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2020) D(0xc007, XILF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2000) +/* INSERT CHARACTER */ + C(0x4300, IC, RX_a, Z, 0, m2_8u, 0, r1_8, mov2, 0) + C(0xe373, ICY, RXY_a, LD, 0, m2_8u, 0, r1_8, mov2, 0) /* INSERT IMMEDIATE */ D(0xc008, IIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2020) D(0xc009, IILF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2000) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bb593f4..2032264 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -283,12 +283,6 @@ static inline void store_reg16(int reg, TCGv_i32 v) #endif } -static inline void store_reg8(int reg, TCGv_i64 v) -{ - /* 8 bit register writes keep the upper bytes */ - tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8); -} - static inline void store_freg32(int reg, TCGv_i32 v) { /* 32 bit register writes keep the lower half */ @@ -1244,7 +1238,7 @@ static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2) static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1, int x2, int b2, int d2) { - TCGv_i64 addr, tmp2, tmp3; + TCGv_i64 addr, tmp2; TCGv_i32 tmp32_1; LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n", @@ -1294,12 +1288,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1, tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s)); tcg_temp_free_i64(tmp2); break; - case 0x73: /* ICY R1,D2(X2,B2) [RXY] */ - tmp3 = tcg_temp_new_i64(); - tcg_gen_qemu_ld8u(tmp3, addr, get_mem_index(s)); - store_reg8(r1, tmp3); - tcg_temp_free_i64(tmp3); - break; default: LOG_DISAS("illegal e3 operation 0x%x\n", op); gen_illegal_opcode(s); @@ -2383,15 +2371,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) LOG_DISAS("opc 0x%x\n", opc); switch (opc) { - case 0x43: /* IC R1,D2(X2,B2) [RX] */ - insn = ld_code4(env, s->pc); - tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); - tmp2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); - store_reg8(r1, tmp2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; case 0x44: /* EX R1,D2(X2,B2) [RX] */ insn = ld_code4(env, s->pc); tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); @@ -3922,6 +3901,12 @@ static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o) store_reg(get_field(f, r1), o->out); } +static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o) +{ + int r1 = get_field(f, r1); + tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8); +} + static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o) { store_reg32_i64(get_field(f, r1), o->out); @@ -4180,6 +4165,12 @@ static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o) o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2); } +static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o) +{ + in2_a2(s, f, o); + tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s)); +} + static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o) { in2_a2(s, f, o);