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Violators will be prosecuted; Thu, 27 Sep 2012 18:42:31 -0400 Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by d01relay01.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q8RMgUsZ137178 for ; Thu, 27 Sep 2012 18:42:31 -0400 Received: from d01av04.pok.ibm.com (loopback [127.0.0.1]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q8RMgUsl002927 for ; Thu, 27 Sep 2012 18:42:30 -0400 Received: from ibm-tiger.the-meissners.org ([9.33.48.180]) by d01av04.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q8RMgUQp002830; Thu, 27 Sep 2012 18:42:30 -0400 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 5B404425A4; Thu, 27 Sep 2012 18:42:28 -0400 (EDT) Date: Thu, 27 Sep 2012 18:42:28 -0400 From: Michael Meissner To: David Edelsohn , gcc-patches@gcc.gnu.org, bergner@vnet.ibm.com, segher@kernel.crashing.org, iain@codesourcery.com, andreast-list@fgznet.ch Subject: Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b Message-ID: <20120927224228.GA24889@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , David Edelsohn , gcc-patches@gcc.gnu.org, bergner@vnet.ibm.com, segher@kernel.crashing.org, iain@codesourcery.com, andreast-list@fgznet.ch References: <20120912224303.GA19348@ibm-tiger.the-meissners.org> <20120917195131.GA22648@ibm-tiger.the-meissners.org> <20120920195755.GA18581@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20120920195755.GA18581@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) x-cbid: 12092722-6078-0000-0000-0000101553BB X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org (Lets try this again, this time attaching the said patch). This patch fixes a long standing bug that David noticed, namely if you don't use -mcpu=, the target options that are set by the configuration .h files in TARGET_DEFAULT are cleared if they are in POWERPC_MASKS. Note, if you configure the compiler using --with-cpu=, it provides a default cpu, so users using pre-packaged compilers, typically would not see the bug. In adding the support for the above change, I also tweaked the debug output for -mdebug=reg so it prints more information about the switches set. Other than that, this is the same patch that I previously submitted. I have done the bootstrap and make check with no regressions. I have also built special compilers without --with-cpu to make sure the changes were correctly propigated. Are these patches ok to install? 2012-09-27 Michael Meissner * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Move all switches that set target_flags to set rs6000_isa_flags, and make it HOST_WIDE_INT. Save/restore new option words. Add TARGET_ maps for OPTION_. Add MASK_ maps for OPTION_MASK_. Print more debug output for -mdebug=reg. Move masks for different cpu levels to rs6000-cpus.def. Turn off VSX if the assembler doesn't support Altivec. Change #ifdef TARGET_ to #ifdef OPTION_. If no -mcpu= was used, use all of the bits in TARGET_DEFAULT for the isa bits. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * gcc/config/rs6000/darwin.opt (-m64): Likewise. (-m32): Likewise. * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * gcc/config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. * gcc/config/rs6000/rs6000-protos.h (rs6000_builtin_mask_calculate): Likewise. (rs6000_target_modify_macros): Likewise. (rs6000_target_modify_macros_ptr): Likewise. * gcc/config/rs6000/rs6000.c (struct builtin_description): Likewise. (rs6000_target_modify_macros_ptr): Likewise. (struct rs6000_builtin_info): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (OPTION_MASK_STRICT_ALIGN): Likewise. (struct rs6000_ptt): Likewise. (DEBUG_FMT_ID): Likewise. (DEBUG_FMT_D): Likewise. (DEBUG_FMT_X): Likewise. (DEBUG_FMT_WX): Likewise. (DEBUG_FMT_WX2): Likewise. (DEBUG_FMT_S): Likewise. (rs6000_debug_reg_global): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_builtin_mask_calculate): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (paired_expand_builtin): Likewise. (spe_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_builtin_decl): Likewise. (rs6000_common_init_builtins): Likewise. (rs6000_darwin_file_start): Likewise. (struct rs6000_opt_mask): Likewise. (rs6000_opt_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_print_isa_or_misc_options): Likewise. (rs6000_print_isa_options): Likewise. (rs6000_can_inline_p): Likewise. * gcc/config/rs6000/rs6000.h (MASK_64BIT): Likewise. (MASK_ALTIVEC): Likewise. (MASK_CMPB): Likewise. (MASK_DFP): Likewise. (MASK_DLMZB): Likewise. (MASK_EABI): Likewise. (MASK_FPRND): Likewise. (MASK_HARD_FLOAT): Likewise. (MASK_ISEL): Likewise. (MASK_LITTLE_ENDIAN): Likewise. (MASK_MFCRF): Likewise. (MASK_MFPGPR): Likewise. (MASK_MINIMAL_TOC): Likewise. (MASK_MULHW): Likewise. (MASK_MULTIPLE): Likewise. (MASK_NO_UPDATE): Likewise. (MASK_POPCNTB): Likewise. (MASK_POPCNTD): Likewise. (MASK_POWERPC64): Likewise. (MASK_PPC_GFXOPT): Likewise. (MASK_PPC_GPOPT): Likewise. (MASK_PROTOTYPE): Likewise. (MASK_RECIP_PRECISION): Likewise. (MASK_REGNAMES): Likewise. (MASK_RELOCATABLE): Likewise. (MASK_SOFT_FLOAT): Likewise. (MASK_STRICT_ALIGN): Likewise. (MASK_STRING): Likewise. (MASK_UPDATE): Likewise. (MASK_VSX): Likewise. (OPTION_CMPB): Likewise. (OPTION_DFP): LIkewise. (OPTION_FPRND): Likewise. (OPTION_MFCRF): Likewise. (OPTION_MFPGPR): Likewise. (OPTION_POPCNTB): Likewise. (OPTION_POPCNTD): Likewise. (TARGET_64BIT): Likewise. (TARGET_ALTIVEC): Likewise. (TARGET_CMPB): Likewise. (TARGET_DFP): Likewise. (TARGET_DLMZB): Likewise. (TARGET_EABI): Likewise. (TARGET_FPRND): Likewise. (TARGET_HARD_FLOAT): Likewise. (TARGET_ISEL): Likewise. (TARGET_LITTLE_ENDIAN): Likewise. (TARGET_MFCRF): Likewise. (TARGET_MFPGPR): Likewise. (TARGET_MINIMAL_TOC): Likewise. (TARGET_MULHW): Likewise. (TARGET_MULTIPLE): Likewise. (TARGET_NO_UPDATE): Likewise. (TARGET_POPCNTB): Likewise. (TARGET_POPCNTD): Likewise. (TARGET_POWERPC64): Likewise. (TARGET_PPC_GFXOPT): Likewise. (TARGET_PPC_GPOPT): Likewise. (TARGET_PROTOTYPE): Likewise. (TARGET_RECIP_PRECISION): Likewise. (TARGET_REGNAMES): Likewise. (TARGET_RELOCATABLE): Likewise. (TARGET_SOFT_FLOAT): Likewise. (TARGET_STRICT_ALIGN): Likewise. (TARGET_STRING): Likewise. (TARGET_UPDATE): Likewise. (TARGET_VSX): Likewise. * gcc/config/rs6000/rs6000.opt (rs6000_isa_flags): Likewise. (x_rs6000_isa_flags): Likewise. (x_rs6000_ins_flags_explicit): Likewise. (rs6000_builtin_mask): Likewise. (target_flags_explicit): Likewise. (-mpowerpc64): Likewise. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. (-mpopcntb): Likewise. (-mfprnd): Likewise. (-mcmpb): Likewise. (-mmfpgpr): Likewise. (-maltivec): Likewise. (-mhard-dfp): Likewise. (-mmulhw): Likewise. (-mdlmzb): Likewise. (-mmultiple): Likewise. (-mstring): Likewise. (-msoft-float): Likewise. (-mhard-float): Likewise. (-mpopcntd): Likewise. (-mvsx): Likewise. (-mno-update): Likewise. (-mupdate): Likewise. (-mrecip-precision): Likewise. (-mminimal-toc): Likewise. (-misel): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * gcc/config/rs6000/sysv4.opt (-mstrict-align): Likewise. (-mrelocatable): Likewise. (-mlittle-endian): Likewise. (-mlittle): Likewise. (-mbig-endian): Likewise. (-mbig): Likewise. (-meabi): Likewise. (-m64): Likewise. (-m32): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def dependency. Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 191811) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -82,23 +82,23 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +107,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,8 +118,8 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: @@ -181,8 +182,8 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 1; } break; @@ -190,14 +191,16 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); opts->x_TARGET_NO_FP_IN_TOC = 1; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -227,15 +230,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,8 +262,8 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_xilinx_fpu = 1; if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; @@ -272,8 +275,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -297,8 +300,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 191811) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 191811) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 191811) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 191811) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 191811) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 191811) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -285,38 +285,42 @@ rs6000_define_or_undefine_macro (bool de have both the target flags and the builtin flags as arguments. */ void -rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, + HOST_WIDE_INT bu_mask) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n", + fprintf (stderr, + "rs6000_target_modify_macros (%s, " + HOST_WIDE_INT_PRINT_HEX ", " + HOST_WIDE_INT_PRINT_HEX ")\n", (define_p) ? "define" : "undef", - (unsigned) flags, bu_mask); + flags, bu_mask); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -326,7 +330,7 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ @@ -342,7 +346,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, + rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_builtin_mask_calculate ()); if (TARGET_FRE) Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 191811) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,17 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -80,86 +91,82 @@ unsigned int rs6000_recip_control ;; Mask of what builtin functions are allowed TargetVariable -unsigned int rs6000_builtin_mask +HOST_WIDE_INT rs6000_builtin_mask ;; Debug flags TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction mfriz @@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_ Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double @@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base @@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +292,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 191811) +++ gcc/config/rs6000/linux64.h (working copy) @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,14 +103,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -118,12 +118,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 191811) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -213,7 +213,7 @@ static GTY(()) section *toc_section; struct builtin_description { - const unsigned int mask; + const HOST_WIDE_INT mask; const enum insn_code icode; const char *const name; const enum rs6000_builtins code; @@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); /* Target cpu costs. */ @@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = { struct rs6000_builtin_info_type { const char *name; const enum insn_code icode; - const unsigned mask; + const HOST_WIDE_INT mask; const unsigned attr; }; @@ -1015,6 +1015,9 @@ bool (*rs6000_cannot_change_mode_class_p const int INSN_NOT_AVAILABLE = -1; +static void rs6000_print_isa_options (FILE *, int, const char *, + HOST_WIDE_INT); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct @@ -1115,7 +1118,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL @@ -1458,53 +1462,12 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ const enum processor_type processor; /* Processor type enum value. */ - const int target_enable; /* Target flags to enable. */ + const HOST_WIDE_INT target_enable; /* Target flags to enable. */ }; static struct rs6000_ptt const processor_target_table[] = @@ -1715,9 +1678,10 @@ rs6000_debug_reg_print (int first_regno, } } -#define DEBUG_FMT_D "%-32s= %d\n" -#define DEBUG_FMT_X "%-32s= 0x%x\n" -#define DEBUG_FMT_S "%-32s= %s\n" +#define DEBUG_FMT_ID "%-32s= " +#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" +#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: " +#define DEBUG_FMT_S DEBUG_FMT_ID "%s\n" /* Print various interesting information with -mdebug=reg. */ static void @@ -1728,11 +1692,13 @@ rs6000_debug_reg_global (void) int m; char costly_num[20]; char nop_num[20]; + char flags_buffer[40]; const char *costly_str; const char *nop_str; const char *trace_str; const char *abi_str; const char *cmodel_str; + struct cl_target_option cl_opts; /* Map enum rs6000_vector to string. */ static const char *rs6000_debug_vector_unit[] = { @@ -1812,12 +1778,42 @@ rs6000_debug_reg_global (void) } if (rs6000_cpu_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "cpu", - processor_target_table[rs6000_cpu_index].name); + { + const char *name = processor_target_table[rs6000_cpu_index].name; + HOST_WIDE_INT flags + = processor_target_table[rs6000_cpu_index].target_enable; + + sprintf (flags_buffer, "-mcpu=%s flags", name); + rs6000_print_isa_options (stderr, 0, flags_buffer, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "cpu", ""); if (rs6000_tune_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "tune", - processor_target_table[rs6000_tune_index].name); + { + const char *name = processor_target_table[rs6000_tune_index].name; + HOST_WIDE_INT flags + = processor_target_table[rs6000_tune_index].target_enable; + + sprintf (flags_buffer, "-mtune=%s flags", name); + rs6000_print_isa_options (stderr, 0, flags_buffer, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "tune", ""); + + cl_target_option_save (&cl_opts, &global_options); + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags", rs6000_isa_flags); + + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); + + rs6000_print_isa_options (stderr, 0, "rs6000_builtin_mask", + rs6000_builtin_mask); + + rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT); + + fprintf (stderr, DEBUG_FMT_S, "--with-cpu default", + OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : ""); switch (rs6000_sched_costly_dep) { @@ -1935,7 +1931,15 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + + fprintf (stderr, DEBUG_FMT_S, "plt-format", + TARGET_SECURE_PLT ? "secure" : "bss"); + fprintf (stderr, DEBUG_FMT_S, "struct-return", + aix_struct_return ? "aix" : "sysv"); fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]); + fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]); fprintf (stderr, DEBUG_FMT_S, "align_branch", tf[!!rs6000_align_branch_targets]); fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size); @@ -1947,7 +1951,6 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); - fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask); } /* Initialize the various global tables that are based on register size. */ @@ -2311,21 +2314,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2333,10 +2336,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2353,7 +2356,7 @@ darwin_rs6000_override_options (void) bits, and some options like SPE and PAIRED are no longer in target_flags. */ -unsigned +HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) @@ -2380,7 +2383,7 @@ rs6000_option_override_internal (bool gl /* The default cpu requested at configure time, if any. */ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; - int set_masks; + HOST_WIDE_INT set_masks; int cpu_index; int tune_index; struct cl_target_option *main_target_opt @@ -2417,18 +2420,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu= and -mtune= argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2457,9 +2466,14 @@ rs6000_option_override_internal (bool gl gcc_assert (cpu_index >= 0); - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); + + /* If no -mcpu=, inherit any default options that were cleared via + POWERPC_MASKS. */ + if (!have_cpu) + rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2544,7 +2558,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2556,15 +2571,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2576,10 +2591,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2590,9 +2605,10 @@ rs6000_option_override_internal (bool gl msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2601,27 +2617,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-