From patchwork Thu Sep 27 13:24:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 187396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4B8EA2C00AC for ; Fri, 28 Sep 2012 01:07:50 +1000 (EST) Received: from localhost ([::1]:51861 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE6v-0003dg-Vc for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 09:26:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:46014) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE6U-0003DN-29 for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:26:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THE6R-00032Z-1K for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:26:09 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:50861) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE6Q-00032T-LF for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:26:06 -0400 Received: by dadn15 with SMTP id n15so390658dad.4 for ; Thu, 27 Sep 2012 06:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=lBVi5E9TbuTlj6r0kmkiowrW7YrHpQbyeVj2P4Q3mtA=; b=CbmWxS1p67EMlROhC9j4MOdF7ZMi+3DMkUB5vmJHjBVmvBXrrIv76fxNBWNhzMnewO M7Xsjf1UbQci8BZvhV/kiMLmwwXu42XQqEU1CKxvgF2kDbciyxUSsw8IFO2DmCfQTW9r Nm8pgXbvmvBMU1I7XoJGOgO8C3rTUfT6OM/IaL9V5gCY4q0agfvrORUuxZ/rkPCmZ/77 pzA2vnU6lQCHH0ucJlcruN64vhC0l7iFXaaYt0EU24KJhtRdHjHikpz+m2dtocmdrV5c jiyIyKeEbkS9LyNxZKAX/7Ezx2yX3EsKc5xqDdVEblLV80OJ2cxHkvAvbCAOX9XbuuXi /uqw== Received: by 10.68.240.36 with SMTP id vx4mr11460563pbc.89.1348752365933; Thu, 27 Sep 2012 06:26:05 -0700 (PDT) Received: from localhost.localdomain ([123.150.196.82]) by mx.google.com with ESMTPS id pj8sm3831673pbb.60.2012.09.27.06.25.59 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 06:26:04 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 21:24:47 +0800 Message-Id: <1348752291-6041-11-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.10.2 (Apple Git-33) In-Reply-To: <1348752291-6041-1-git-send-email-proljc@gmail.com> References: <1348752291-6041-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v9 10/14] target-mips-ase-dsp: Add compare-pick instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu --- target-mips/dsp_helper.c | 235 ++++++++++++++++++++++++++++++ target-mips/helper.h | 52 +++++++ target-mips/translate.c | 356 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 643 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 7516242..dabece4 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3241,6 +3241,241 @@ BIT_INSV(dinsv, 0x7F, 0x3F, target_long); #undef BIT_INSV +/** DSP Compare-Pick Sub-class insns **/ +#define CMP_HAS_RET(name, func, split_num, filter, bit_size) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ +{ \ + uint32_t rs_t[split_num]; \ + uint32_t rt_t[split_num]; \ + uint8_t cc[split_num]; \ + uint32_t temp = 0; \ + int i; \ + \ + for (i = 0; i < split_num; i++) { \ + rs_t[i] = (rs >> (bit_size * i)) & filter; \ + rt_t[i] = (rt >> (bit_size * i)) & filter; \ + cc[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \ + temp |= cc[i] << i; \ + } \ + \ + return (target_ulong)temp; \ +} + +CMP_HAS_RET(cmpgu_eq_qb, cmp_eq, 4, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_lt_qb, cmp_lt, 4, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_le_qb, cmp_le, 4, MIPSDSP_Q0, 8); + +#ifdef TARGET_MIPS64 +CMP_HAS_RET(cmpgu_eq_ob, cmp_eq, 8, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_lt_ob, cmp_lt, 8, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_le_ob, cmp_le, 8, MIPSDSP_Q0, 8); +#endif + +#undef CMP_HAS_RET + + +#define CMP_NO_RET(name, func, split_num, filter, bit_size) \ +void helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int32_t rs_t[split_num], rt_t[split_num]; \ + int32_t flag = 0; \ + int32_t cc[split_num]; \ + int i; \ + \ + for (i = 0; i < split_num; i++) { \ + rs_t[i] = (rs >> (bit_size * i)) & filter; \ + rt_t[i] = (rt >> (bit_size * i)) & filter; \ + \ + cc[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \ + flag |= cc[i] << i; \ + } \ + \ + set_DSPControl_24(flag, split_num, env); \ +} + +CMP_NO_RET(cmpu_eq_qb, cmp_eq, 4, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_lt_qb, cmp_lt, 4, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_le_qb, cmp_le, 4, MIPSDSP_Q0, 8); + +CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16); + +#ifdef TARGET_MIPS64 +CMP_NO_RET(cmpu_eq_ob, cmp_eq, 8, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_lt_ob, cmp_lt, 8, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_le_ob, cmp_le, 8, MIPSDSP_Q0, 8); + +CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16); + +CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32); +CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32); +CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32); +#endif +#undef CMP_NO_RET + +#if defined(TARGET_MIPS64) + +#define CMPGDU_OB(name) \ +target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int i; \ + uint8_t rs_t[8], rt_t[8]; \ + uint32_t cond; \ + \ + cond = 0; \ + \ + for (i = 0; i < 8; i++) { \ + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ + \ + if (mipsdsp_cmp_##name(rs_t[i], rt_t[i])) { \ + cond |= 0x01 << i; \ + } \ + } \ + \ + set_DSPControl_24(cond, 8, env); \ + \ + return (uint64_t)cond; \ +} + +CMPGDU_OB(eq) +CMPGDU_OB(lt) +CMPGDU_OB(le) +#undef CMPGDU_OB +#endif + +#define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint32_t rs_t[split_num]; \ + uint32_t rt_t[split_num]; \ + uint32_t cc[split_num]; \ + target_ulong dsp; \ + int i; \ + target_ulong result = 0; \ + \ + dsp = env->active_tc.DSPControl; \ + for (i = 0; i < split_num; i++) { \ + rs_t[i] = (rs >> (bit_size * i)) & filter; \ + rt_t[i] = (rt >> (bit_size * i)) & filter; \ + cc[i] = (dsp >> (24 + i)) & 0x01; \ + cc[i] = cc[i] == 1 ? rs_t[i] : rt_t[i]; \ + \ + result |= (target_ulong)cc[i] << (bit_size * i); \ + } \ + \ + if (ret32bit) { \ + result = (target_long)(int32_t)(result & MIPSDSP_LLO); \ + } \ + \ + return result; \ +} + +PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1); +PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1); + +#ifdef TARGET_MIPS64 +PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0); +PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0); +PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0); +#endif +#undef PICK_INSN + +#define APPEND_INSN(name, ret_32) \ +target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \ +{ \ + target_ulong temp; \ + \ + if (ret_32) { \ + temp = ((rt & MIPSDSP_LLO) << sa) | \ + ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \ + temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \ + } else { \ + temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \ + } \ + \ + return temp; \ +} + +APPEND_INSN(append, 1); +#ifdef TARGET_MIPS64 +APPEND_INSN(dappend, 0); +#endif +#undef APPEND_INSN + +#define PREPEND_INSN(name, or_val, ret_32) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + uint32_t sa) \ +{ \ + sa |= or_val; \ + \ + if (1) { \ + return (target_long)(int32_t)(uint32_t) \ + (((rs & MIPSDSP_LLO) << (32 - sa)) | \ + ((rt & MIPSDSP_LLO) >> sa)); \ + } else { \ + return (rs << (64 - sa)) | (rt >> sa); \ + } \ +} + +PREPEND_INSN(prepend, 0, 1); +#ifdef TARGET_MIPS64 +PREPEND_INSN(prependw, 0, 0); +PREPEND_INSN(prependd, 0x20, 0); +#endif +#undef PREPEND_INSN + +#define BALIGN_INSN(name, filter, ret32) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \ +{ \ + bp = bp & 0x03; \ + \ + if ((bp & 1) == 0) { \ + return rt; \ + } else { \ + if (ret32) { \ + return (target_long)(int32_t)((rt << (8 * bp)) | \ + (rs >> (8 * (4 - bp)))); \ + } else { \ + return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \ + } \ + } \ +} + +BALIGN_INSN(balign, 0x03, 1); +#if defined(TARGET_MIPS64) +BALIGN_INSN(dbalign, 0x07, 0); +#endif +#undef BALIGN_INSN + +target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt) +{ + uint32_t rsl, rth; + + rsl = rs & MIPSDSP_LO; + rth = (rt & MIPSDSP_HI) >> 16; + + return (target_long)(int32_t)((rsl << 16) | rth); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt) +{ + uint32_t rs0, rt1; + + rs0 = rs & MIPSDSP_LLO; + rt1 = (rt >> 32) & MIPSDSP_LLO; + + return ((uint64_t)rs0 << 32) | (uint64_t)rt1; +} +#endif + #undef MIPSDSP_LHI #undef MIPSDSP_LLO #undef MIPSDSP_HI diff --git a/target-mips/helper.h b/target-mips/helper.h index 31475a2..3d3c596 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -624,4 +624,56 @@ DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl); #endif +/* DSP Compare-Pick Sub-class insns */ +DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(append, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dappend, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +#endif +DEF_HELPER_FLAGS_3(prepend, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(prependd, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +DEF_HELPER_FLAGS_3(prependw, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +#endif +DEF_HELPER_FLAGS_3(balign, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dbalign, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32) +#endif +DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) +#endif + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index d5c2419..7102074 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -348,6 +348,11 @@ enum { #if defined(TARGET_MIPS64) OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, #endif + /* MIPS DSP Compare-Pick Sub-class */ + OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, +#endif }; /* BSHFL opcodes */ @@ -473,6 +478,22 @@ enum { OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, + /* DSP Compare-Pick Sub-class */ + OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP, }; #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -535,6 +556,14 @@ enum { OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, }; +#define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Compare-Pick Sub-class */ + OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, + OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, + OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, +}; + #if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -603,6 +632,26 @@ enum { #if defined(TARGET_MIPS64) #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { + /* DSP Compare-Pick Sub-class */ + OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP, /* MIPS DSP Arithmetic Sub-class */ OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, @@ -616,6 +665,17 @@ enum { #endif #if defined(TARGET_MIPS64) +#define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* DSP Compare-Pick Sub-class */ + OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, + OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, + OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, + OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, +}; +#endif + +#if defined(TARGET_MIPS64) #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* DSP Bit/Manipulation Sub-class */ @@ -13897,6 +13957,250 @@ static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx, MIPS_DEBUG("%s", opn); } +static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, + uint32_t op1, uint32_t op2, + int ret, int v1, int v2, int check_ret) +{ + const char *opn = "mipsdsp add compare pick"; + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv t1 = tcg_temp_new(); + + if ((ret == 0) && (check_ret == 1)) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + switch (op1) { + case OPC_APPEND_DSP: + switch (op2) { + case OPC_APPEND: + tcg_gen_movi_i32(t0, v2); + gen_helper_append(cpu_gpr[ret], cpu_gpr[ret], + cpu_gpr[v1], t0); + break; + case OPC_PREPEND: + tcg_gen_movi_i32(t0, v2); + gen_helper_prepend(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[ret], t0); + break; + case OPC_BALIGN: + tcg_gen_movi_i32(t0, v2); + gen_helper_balign(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[ret], t0); + break; + default: /* Invid */ + MIPS_INVAL("MASK APPEND"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_CMPU_EQ_QB_DSP: + switch (op2) { + case OPC_CMPU_EQ_QB: + check_dsp(ctx); + gen_helper_cmpu_eq_qb(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMPU_LT_QB: + check_dsp(ctx); + gen_helper_cmpu_lt_qb(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMPU_LE_QB: + check_dsp(ctx); + gen_helper_cmpu_le_qb(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMPGU_EQ_QB: + check_dsp(ctx); + gen_helper_cmpgu_eq_qb(cpu_gpr[ret], cpu_gpr[v1], cpu_gpr[v2]); + break; + case OPC_CMPGU_LT_QB: + check_dsp(ctx); + gen_helper_cmpgu_lt_qb(cpu_gpr[ret], cpu_gpr[v1], cpu_gpr[v2]); + break; + case OPC_CMPGU_LE_QB: + check_dsp(ctx); + gen_helper_cmpgu_le_qb(cpu_gpr[ret], cpu_gpr[v1], cpu_gpr[v2]); + break; + case OPC_CMPGDU_EQ_QB: + check_dspr2(ctx); + gen_helper_cmpgu_eq_qb(t1, cpu_gpr[v1], cpu_gpr[v2]); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMPGDU_LT_QB: + check_dspr2(ctx); + gen_helper_cmpgu_lt_qb(t1, cpu_gpr[v1], cpu_gpr[v2]); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMPGDU_LE_QB: + check_dspr2(ctx); + gen_helper_cmpgu_le_qb(t1, cpu_gpr[v1], cpu_gpr[v2]); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMP_EQ_PH: + check_dsp(ctx); + gen_helper_cmp_eq_ph(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_LT_PH: + check_dsp(ctx); + gen_helper_cmp_lt_ph(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_LE_PH: + check_dsp(ctx); + gen_helper_cmp_le_ph(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_PICK_QB: + check_dsp(ctx); + gen_helper_pick_qb(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_PICK_PH: + check_dsp(ctx); + gen_helper_pick_ph(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_PACKRL_PH: + check_dsp(ctx); + gen_helper_packrl_ph(cpu_gpr[ret], cpu_gpr[v1], cpu_gpr[v2]); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_CMPU_EQ_OB_DSP: + switch (op2) { + case OPC_CMP_EQ_PW: + check_dsp(ctx); + gen_helper_cmp_eq_pw(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_LT_PW: + check_dsp(ctx); + gen_helper_cmp_lt_pw(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_LE_PW: + check_dsp(ctx); + gen_helper_cmp_le_pw(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_EQ_QH: + check_dsp(ctx); + gen_helper_cmp_eq_qh(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_LT_QH: + check_dsp(ctx); + gen_helper_cmp_lt_qh(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMP_LE_QH: + check_dsp(ctx); + gen_helper_cmp_le_qh(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMPGDU_EQ_OB: + check_dspr2(ctx); + gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_CMPGDU_LT_OB: + check_dspr2(ctx); + gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_CMPGDU_LE_OB: + check_dspr2(ctx); + gen_helper_cmpgdu_le_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_CMPGU_EQ_OB: + check_dsp(ctx); + gen_helper_cmpgu_eq_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2]); + break; + case OPC_CMPGU_LT_OB: + check_dsp(ctx); + gen_helper_cmpgu_lt_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2]); + break; + case OPC_CMPGU_LE_OB: + check_dsp(ctx); + gen_helper_cmpgu_le_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2]); + break; + case OPC_CMPU_EQ_OB: + check_dsp(ctx); + gen_helper_cmpu_eq_ob(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMPU_LT_OB: + check_dsp(ctx); + gen_helper_cmpu_lt_ob(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_CMPU_LE_OB: + check_dsp(ctx); + gen_helper_cmpu_le_ob(cpu_gpr[v1], cpu_gpr[v2], cpu_env); + break; + case OPC_PACKRL_PW: + check_dsp(ctx); + gen_helper_packrl_pw(cpu_gpr[ret], cpu_gpr[v1], cpu_gpr[v2]); + break; + case OPC_PICK_OB: + check_dsp(ctx); + gen_helper_pick_ob(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_PICK_PW: + check_dsp(ctx); + gen_helper_pick_pw(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + case OPC_PICK_QH: + check_dsp(ctx); + gen_helper_pick_qh(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[v2], cpu_env); + break; + } + break; + case OPC_DAPPEND_DSP: + switch (op2) { + case OPC_DAPPEND: + tcg_gen_movi_i32(t0, v2); + gen_helper_dappend(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[ret], t0); + break; + case OPC_PREPENDD: + tcg_gen_movi_i32(t0, v2); + gen_helper_prependd(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[ret], t0); + break; + case OPC_PREPENDW: + tcg_gen_movi_i32(t0, v2); + gen_helper_prependw(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[ret], t0); + break; + case OPC_DBALIGN: + tcg_gen_movi_i32(t0, v2); + gen_helper_dbalign(cpu_gpr[ret], cpu_gpr[v1], + cpu_gpr[ret], t0); + break; + default: /* Invalid */ + MIPS_INVAL("MASK DAPPEND"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#endif + } + + tcg_temp_free_i32(t0); + tcg_temp_free(t1); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} + /* End MIPSDSP functions. */ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) @@ -14388,6 +14692,25 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_PRECRQU_S_QB_PH: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_CMPU_EQ_QB: + case OPC_CMPU_LT_QB: + case OPC_CMPU_LE_QB: + case OPC_CMP_EQ_PH: + case OPC_CMP_LT_PH: + case OPC_CMP_LE_PH: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); + break; + case OPC_CMPGU_EQ_QB: + case OPC_CMPGU_LT_QB: + case OPC_CMPGU_LE_QB: + case OPC_CMPGDU_EQ_QB: + case OPC_CMPGDU_LT_QB: + case OPC_CMPGDU_LE_QB: + case OPC_PICK_QB: + case OPC_PICK_PH: + case OPC_PACKRL_PH: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); + break; default: /* Invalid */ MIPS_INVAL("MASK CMPU.EQ.QB"); generate_exception(ctx, EXCP_RI); @@ -14450,6 +14773,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_APPEND_DSP: + check_dspr2(ctx); + op2 = MASK_APPEND(ctx->opcode); + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -14560,12 +14888,40 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_PRECRQU_S_OB_QH: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_CMPU_EQ_OB: + case OPC_CMPU_LT_OB: + case OPC_CMPU_LE_OB: + case OPC_CMP_EQ_QH: + case OPC_CMP_LT_QH: + case OPC_CMP_LE_QH: + case OPC_CMP_EQ_PW: + case OPC_CMP_LT_PW: + case OPC_CMP_LE_PW: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); + break; + case OPC_CMPGDU_EQ_OB: + case OPC_CMPGDU_LT_OB: + case OPC_CMPGDU_LE_OB: + case OPC_CMPGU_EQ_OB: + case OPC_CMPGU_LT_OB: + case OPC_CMPGU_LE_OB: + case OPC_PACKRL_PW: + case OPC_PICK_OB: + case OPC_PICK_PW: + case OPC_PICK_QH: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); + break; default: /* Invalid */ MIPS_INVAL("MASK CMPU_EQ.OB"); generate_exception(ctx, EXCP_RI); break; } break; + case OPC_DAPPEND_DSP: + check_dspr2(ctx); + op2 = MASK_DAPPEND(ctx->opcode); + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); + break; case OPC_DPAQ_W_QH_DSP: op2 = MASK_DPAQ_W_QH(ctx->opcode); switch (op2) {