From patchwork Thu Sep 27 13:24:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 187395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1050E2C00AF for ; Fri, 28 Sep 2012 01:05:35 +1000 (EST) Received: from localhost ([::1]:38287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THFef-0005w7-4l for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 11:05:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:46085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE6j-0003ca-9C for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:26:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THE6d-000369-2O for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:26:25 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:50861) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE6c-00032T-T3 for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:26:19 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so390658dad.4 for ; Thu, 27 Sep 2012 06:26:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=gTGdhcLpuDiFLc0aR8gA14bfLBCf5BGffLo+B6WHgiY=; b=MchTDFMBh+sOVCIuyIt4So96xNq8G8IMNHK0QvYv7cElVoX1n9MXh6AK9E8WFWsHC/ ywSjIZJnKMImmaXsCWX7aiq9x+dlaE9TSFLBQqSppWxCSKLmfm6eTu4Mj19yp0tiylKL pMJ3xhSu7pSALqcrPBd/Cie2095fKHk41umKzIBhF5sn87efx2146kQReBct59xlJNQG wtmC+tJ4VCrsPeGcKXAWEDsS1v88zQNeiEm9zLFIySzO1/Xds1ZRrKLaEQqZhG1/pWHa pxpJN36vK4Ngi2gDUoXkpesf98BvlLGQji494FP93GA7igtbh5/oe072gUaEKG1ysF8J 8xOw== Received: by 10.68.200.227 with SMTP id jv3mr11229230pbc.162.1348752378583; Thu, 27 Sep 2012 06:26:18 -0700 (PDT) Received: from localhost.localdomain ([123.150.196.82]) by mx.google.com with ESMTPS id pj8sm3831673pbb.60.2012.09.27.06.26.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 06:26:17 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 21:24:49 +0800 Message-Id: <1348752291-6041-13-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.10.2 (Apple Git-33) In-Reply-To: <1348752291-6041-1-git-send-email-proljc@gmail.com> References: <1348752291-6041-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v9 12/14] target-mips-ase-dsp: Add MIPS DSP processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: Jia Liu --- target-mips/translate_init.c | 52 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c39138f..73a14a9 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -311,6 +311,29 @@ static const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, .mmu_type = MMU_TYPE_R4000, }, + { + .name = "74Kf", + .CP0_PRid = 0x97, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name = "R4000", @@ -484,6 +507,35 @@ static const mips_def_t mips_defs[] = .insn_flags = CPU_LOONGSON2F, .mmu_type = MMU_TYPE_R4000, }, + { + /* A generic CPU providing MIPS64 ASE DSP 2 features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "mips64dspr2", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + /* The architectural limit is 59, but we have hardcoded 36 bit + in some places... + .PABITS = 59, */ /* the architectural limit */ + .PABITS = 36, + .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, #endif };