From patchwork Thu Sep 27 13:24:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 187383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 87AC92C009C for ; Fri, 28 Sep 2012 00:27:59 +1000 (EST) Received: from localhost ([::1]:51849 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE6l-0003cb-Tk for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 09:26:27 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE5z-0001ox-7k for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:25:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THE5s-0002jS-Mm for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:25:39 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:55437) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THE5s-0002Ww-7U for qemu-devel@nongnu.org; Thu, 27 Sep 2012 09:25:32 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so3603748pbb.4 for ; Thu, 27 Sep 2012 06:25:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=8pOmJqBuJpswkF5AajB15FyVbeDc1FMcy3r1108cdew=; b=mhGUH1/Ltkakp8J8X6FeIMqu/G1HeiVR8Q+BwEh8+Y8JsA2BFhipdy4hkTx/T/agXg Br7h1wxapVv4rzRqG/5gdyshHX3UnlqnKeQ7OapPbLy8QznDesfS5/Z+gf5xQSj8YXOa G2DcSDQKZxNK/7rxBE41k15b4nFybpyu/QgqINFhJbrS0MHYCzVUecT/9IAFprnJiHo9 Nwut1PSMWvev8Mz560j9uqFsgNYgwOX7SvRFkpZjBNCblb/Qbg8ytIIwSVJA+3IeyM3P RYQeutqvrTtnd2n4FbmnV+juYnxsDsDHs71eJyrLFj5SzRT4M6M3aa74j/75/nXoMJ7z qJWA== Received: by 10.68.225.68 with SMTP id ri4mr11272721pbc.115.1348752331906; Thu, 27 Sep 2012 06:25:31 -0700 (PDT) Received: from localhost.localdomain ([123.150.196.82]) by mx.google.com with ESMTPS id pj8sm3831673pbb.60.2012.09.27.06.25.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 06:25:30 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 21:24:42 +0800 Message-Id: <1348752291-6041-6-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.10.2 (Apple Git-33) In-Reply-To: <1348752291-6041-1-git-send-email-proljc@gmail.com> References: <1348752291-6041-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v9 05/14] target-mips-ase-dsp: Add load instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu --- target-mips/translate.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 4103f24..6d5c475 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -313,6 +313,9 @@ enum { OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, + + /* MIPS DSP Load */ + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, }; /* BSHFL opcodes */ @@ -340,6 +343,17 @@ enum { #endif }; +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +/* MIPS DSP Load */ +enum { + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, +#if defined(TARGET_MIPS64) + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12213,6 +12227,58 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b #endif +/* MIPSDSP functions. */ +static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int base, int offset) +{ + const char *opn = "ldx"; + TCGv t0; + + if (rd == 0 && env->insn_flags & (ASE_DSP | ASE_DSPR2)) { + /* Loongson CPU uses a load to zero register for prefetch. + We emulate it as a NOP. On other CPU we must perform the + actual memory access. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); + save_cpu_state(ctx, 0); + + switch (opc) { + case OPC_LBUX: + op_ld_lbu(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lbux"; + break; + case OPC_LHX: + op_ld_lh(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lhx"; + break; + case OPC_LWX: + op_ld_lw(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lwx"; + break; +#if defined(TARGET_MIPS64) + case OPC_LDX: + op_ld_ld(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "ldx"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s(%s)", opn, + regnames[rd], regnames[offset], regnames[base]); + tcg_temp_free(t0); +} + + +/* End MIPSDSP functions. */ + static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) { int32_t offset; @@ -12568,6 +12634,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_LX_DSP: + check_dsp(ctx); + op2 = MASK_LX(ctx->opcode); + switch (op2) { +#if defined(TARGET_MIPS64) + case OPC_LDX: +#endif + case OPC_LBUX: + case OPC_LHX: + case OPC_LWX: + gen_mipsdsp_ld(env, ctx, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK LX"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: