Message ID | 1348752291-6041-6-git-send-email-proljc@gmail.com |
---|---|
State | New |
Headers | show |
On Thu, Sep 27, 2012 at 09:24:42PM +0800, Jia Liu wrote: > Add MIPS ASE DSP Load instructions. > > Signed-off-by: Jia Liu <proljc@gmail.com> > --- > target-mips/translate.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 84 insertions(+) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 4103f24..6d5c475 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -313,6 +313,9 @@ enum { > OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, > OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, > OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, > + > + /* MIPS DSP Load */ > + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, > }; > > /* BSHFL opcodes */ > @@ -340,6 +343,17 @@ enum { > #endif > }; > > +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) > +/* MIPS DSP Load */ > +enum { > + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, > + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, > + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, > +#if defined(TARGET_MIPS64) > + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, > +#endif > +}; > + > /* Coprocessor 0 (rs field) */ > #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) > > @@ -12213,6 +12227,58 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b > > #endif > > +/* MIPSDSP functions. */ > +static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, > + int rd, int base, int offset) > +{ > + const char *opn = "ldx"; > + TCGv t0; > + > + if (rd == 0 && env->insn_flags & (ASE_DSP | ASE_DSPR2)) { > + /* Loongson CPU uses a load to zero register for prefetch. > + We emulate it as a NOP. On other CPU we must perform the > + actual memory access. */ > + MIPS_DEBUG("NOP"); > + return; > + } I don't really understand why Loongson is playing a role there. This part should simply be dropped. > + t0 = tcg_temp_new(); > + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); base or offset can be register 0, in that case it won't work. > + save_cpu_state(ctx, 0); > + > + switch (opc) { > + case OPC_LBUX: > + op_ld_lbu(t0, t0, ctx); > + gen_store_gpr(t0, rd); > + opn = "lbux"; > + break; > + case OPC_LHX: > + op_ld_lh(t0, t0, ctx); > + gen_store_gpr(t0, rd); > + opn = "lhx"; > + break; > + case OPC_LWX: > + op_ld_lw(t0, t0, ctx); > + gen_store_gpr(t0, rd); > + opn = "lwx"; > + break; > +#if defined(TARGET_MIPS64) > + case OPC_LDX: > + op_ld_ld(t0, t0, ctx); > + gen_store_gpr(t0, rd); > + opn = "ldx"; > + break; > +#endif > + } > + (void)opn; /* avoid a compiler warning */ > + MIPS_DEBUG("%s %s, %s(%s)", opn, > + regnames[rd], regnames[offset], regnames[base]); > + tcg_temp_free(t0); > +} > + > + > +/* End MIPSDSP functions. */ > + > static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) > { > int32_t offset; > @@ -12568,6 +12634,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) > check_insn(env, ctx, INSN_LOONGSON2E); > gen_loongson_integer(ctx, op1, rd, rs, rt); > break; > + case OPC_LX_DSP: > + check_dsp(ctx); As ctx is passed to gen_mipsdsp_ld(), the check might be moved there. > + op2 = MASK_LX(ctx->opcode); > + switch (op2) { > +#if defined(TARGET_MIPS64) > + case OPC_LDX: > +#endif > + case OPC_LBUX: > + case OPC_LHX: > + case OPC_LWX: > + gen_mipsdsp_ld(env, ctx, op2, rd, rs, rt); > + break; > + default: /* Invalid */ > + MIPS_INVAL("MASK LX"); > + generate_exception(ctx, EXCP_RI); > + break; > + } > + break; > #if defined(TARGET_MIPS64) > case OPC_DEXTM ... OPC_DEXT: > case OPC_DINSM ... OPC_DINS: > -- > 1.7.10.2 (Apple Git-33) > >
diff --git a/target-mips/translate.c b/target-mips/translate.c index 4103f24..6d5c475 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -313,6 +313,9 @@ enum { OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, + + /* MIPS DSP Load */ + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, }; /* BSHFL opcodes */ @@ -340,6 +343,17 @@ enum { #endif }; +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +/* MIPS DSP Load */ +enum { + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, +#if defined(TARGET_MIPS64) + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12213,6 +12227,58 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b #endif +/* MIPSDSP functions. */ +static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int base, int offset) +{ + const char *opn = "ldx"; + TCGv t0; + + if (rd == 0 && env->insn_flags & (ASE_DSP | ASE_DSPR2)) { + /* Loongson CPU uses a load to zero register for prefetch. + We emulate it as a NOP. On other CPU we must perform the + actual memory access. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); + save_cpu_state(ctx, 0); + + switch (opc) { + case OPC_LBUX: + op_ld_lbu(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lbux"; + break; + case OPC_LHX: + op_ld_lh(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lhx"; + break; + case OPC_LWX: + op_ld_lw(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lwx"; + break; +#if defined(TARGET_MIPS64) + case OPC_LDX: + op_ld_ld(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "ldx"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s(%s)", opn, + regnames[rd], regnames[offset], regnames[base]); + tcg_temp_free(t0); +} + + +/* End MIPSDSP functions. */ + static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) { int32_t offset; @@ -12568,6 +12634,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_LX_DSP: + check_dsp(ctx); + op2 = MASK_LX(ctx->opcode); + switch (op2) { +#if defined(TARGET_MIPS64) + case OPC_LDX: +#endif + case OPC_LBUX: + case OPC_LHX: + case OPC_LWX: + gen_mipsdsp_ld(env, ctx, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK LX"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS:
Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu <proljc@gmail.com> --- target-mips/translate.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+)