diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index 4fe66fa..05ef1f2 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c @@ -1,5 +1,6 @@ /* * Freescale MPC85xx Memory Controller kenel module + * Copyright (c) 2012 Freescale Semiconductor, Inc. * * Author: Dave Jiang * @@ -21,6 +22,7 @@ #include #include +#include #include "edac_module.h" #include "edac_core.h" #include "mpc85xx_edac.h" @@ -37,11 +39,6 @@ static u32 orig_ddr_err_sbe; /* * PCI Err defines */ -#ifdef CONFIG_PCI -static u32 orig_pci_err_cap_dr; -static u32 orig_pci_err_en; -#endif - static u32 orig_l2_err_disable; #ifdef CONFIG_FSL_SOC_BOOKE static u32 orig_hid1[2]; @@ -163,37 +160,52 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) { struct mpc85xx_pci_pdata *pdata = pci->pvt_info; u32 err_detect; + struct ccsr_pci *reg = pdata->pci_reg; + + err_detect = in_be32(&pdata->pci_reg->pex_err_dr); + + if (pdata->pcie_flag) { + pr_err("PCIE error(s) detected\n"); + pr_err("PCIE ERR_DR register: 0x%08x\n", err_detect); + pr_err("PCIE ERR_CAP_STAT register: 0x%08x\n", + in_be32(®->pex_err_cap_stat)); + pr_err("PCIE ERR_CAP_R0 register: 0x%08x\n", + in_be32(®->pex_err_cap_r0)); + pr_err("PCIE ERR_CAP_R1 register: 0x%08x\n", + in_be32(®->pex_err_cap_r1)); + pr_err("PCIE ERR_CAP_R2 register: 0x%08x\n", + in_be32(®->pex_err_cap_r2)); + pr_err("PCIE ERR_CAP_R3 register: 0x%08x\n", + in_be32(®->pex_err_cap_r3)); + } else { + /* master aborts can happen during PCI config cycles */ + if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { + out_be32(®->pex_err_dr, err_detect); + return; + } - err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); - - /* master aborts can happen during PCI config cycles */ - if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); - return; + pr_err("PCI error(s) detected\n"); + pr_err("PCI/X ERR_DR register: 0x%08x\n", err_detect); + pr_err("PCI/X ERR_ATTRIB register: 0x%08x\n", + in_be32(®->pex_err_attrib)); + pr_err("PCI/X ERR_ADDR register: 0x%08x\n", + in_be32(®->pex_err_disr)); + pr_err("PCI/X ERR_EXT_ADDR register: 0x%08x\n", + in_be32(®->pex_err_ext_addr)); + pr_err("PCI/X ERR_DL register: 0x%08x\n", + in_be32(®->pex_err_dl)); + pr_err("PCI/X ERR_DH register: 0x%08x\n", + in_be32(®->pex_err_dh)); + + if (err_detect & PCI_EDE_PERR_MASK) + edac_pci_handle_pe(pci, pci->ctl_name); + + if (err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_PERR_MASK)) + edac_pci_handle_npe(pci, pci->ctl_name); } - printk(KERN_ERR "PCI error(s) detected\n"); - printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); - - printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); - printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); - printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); - printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); - printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", - in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); - /* clear error bits */ - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); - - if (err_detect & PCI_EDE_PERR_MASK) - edac_pci_handle_pe(pci, pci->ctl_name); - - if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) - edac_pci_handle_npe(pci, pci->ctl_name); + out_be32(®->pex_err_dr, err_detect); } static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) @@ -202,7 +214,7 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) struct mpc85xx_pci_pdata *pdata = pci->pvt_info; u32 err_detect; - err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); + err_detect = in_be32(&pdata->pci_reg->pex_err_dr); if (!err_detect) return IRQ_NONE; @@ -212,11 +224,102 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) return IRQ_HANDLED; } +/* + * This function is for error interrupt ORed mechanism. + * This mechanism attaches most functions' error interrupts to interrupt 0. + * And report error interrupt to mpic via interrupt 0. + * EIMR0 - Error Interrupt Mask Register 0. + * + * This function check whether the device support error interrupt ORed + * mechanism via device tree. If supported, umask pcie error interrupt + * bit in EIMR0. + */ +static int mpc85xx_err_int_en(struct platform_device *op) +{ + u32 *int_cell; + struct device_node *np; + void __iomem *mpic_base; + u32 reg_tmp; + u32 int_len; + struct resource r; + int res; + + if (!op->dev.of_node) + return -EINVAL; + + /* + * Unmask pcie error interrupt bit in EIMR0. + * Extend interrupt specifier has 4 cells. + * For the 3rd cell: + * 0 -- normal interrupt; + * 1 -- error interrupt. + */ + int_cell = (u32 *)of_get_property(op->dev.of_node, "interrupts", + &int_len); + if ((int_len/sizeof(u32)) == 4) { + /* soc has error interrupt integration handling mechanism */ + if (*(int_cell + 2) == 1) { + np = of_find_node_by_type(NULL, "open-pic"); + + if (of_address_to_resource(np, 0, &r)) { + pr_err("%s: Failed to map mpic regs\n", + __func__); + of_node_put(np); + res = -ENOMEM; + goto err; + } + + if (!request_mem_region(r.start, r.end - r.start + 1, + "mpic")) { + pr_err("%s: Error when requesting mem region\n", + __func__); + res = -EBUSY; + goto err; + } + + mpic_base = ioremap(r.start, r.end - r.start + 1); + if (!mpic_base) { + pr_err("%s: Unable to map mpic regs\n", + __func__); + res = -ENOMEM; + goto err_ioremap; + } + + reg_tmp = in_be32(mpic_base + MPC85XX_MPIC_EIMR0); + out_be32(mpic_base + MPC85XX_MPIC_EIMR0, reg_tmp & + ~(1 << (31 - *(int_cell + 3)))); + iounmap(mpic_base); + release_mem_region(r.start, r.end - r.start + 1); + of_node_put(np); + } + } + + return 0; + +err_ioremap: + release_mem_region(r.start, r.end - r.start + 1); +err: + return res; +} + +static int mpc85xx_pcie_find_capability(struct device_node *np) +{ + struct pci_controller *hose; + + if (!np) + return -EINVAL; + + hose = pci_find_hose_for_OF_device(np); + + return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); +} + int __devinit mpc85xx_pci_err_probe(struct platform_device *op) { struct edac_pci_ctl_info *pci; struct mpc85xx_pci_pdata *pdata; struct resource r; + struct ccsr_pci *reg; int res = 0; if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) @@ -245,6 +348,9 @@ int __devinit mpc85xx_pci_err_probe(struct platform_device *op) pci->ctl_name = pdata->name; pci->dev_name = dev_name(&op->dev); + if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0) + pdata->pcie_flag = 1; + if (edac_op_state == EDAC_OPSTATE_POLL) pci->edac_check = mpc85xx_pci_check; @@ -256,10 +362,6 @@ int __devinit mpc85xx_pci_err_probe(struct platform_device *op) "PCI err regs\n", __func__); goto err; } - - /* we only need the error registers */ - r.start += 0xe00; - if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), pdata->name)) { printk(KERN_ERR "%s: Error while requesting mem region\n", @@ -268,26 +370,32 @@ int __devinit mpc85xx_pci_err_probe(struct platform_device *op) goto err; } - pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); - if (!pdata->pci_vbase) { + pdata->pci_reg = devm_ioremap(&op->dev, r.start, resource_size(&r)); + if (!pdata->pci_reg) { printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); res = -ENOMEM; goto err; } - orig_pci_err_cap_dr = - in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); - - /* PCI master abort is expected during config cycles */ - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); + if (mpc85xx_err_int_en(op) < 0) + goto err; - orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); + reg = pdata->pci_reg; + /* disable pci/pcie error detect */ + if (pdata->pcie_flag) { + pdata->orig_pci_err_dr = in_be32(®->pex_err_disr); + out_be32(®->pex_err_disr, ~0); + } else { + pdata->orig_pci_err_dr = in_be32(®->pex_err_cap_dr); + out_be32(®->pex_err_cap_dr, ~0); + } - /* disable master abort reporting */ - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); + /* disable all pcie error interrupt */ + pdata->orig_pci_err_en = in_be32(®->pex_err_en); + out_be32(®->pex_err_en, 0); - /* clear error bits */ - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); + /* clear all error bits */ + out_be32(®->pex_err_dr, ~0); if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { edac_dbg(3, "failed edac_pci_add_device()\n"); @@ -297,7 +405,7 @@ int __devinit mpc85xx_pci_err_probe(struct platform_device *op) if (edac_op_state == EDAC_OPSTATE_INT) { pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); res = devm_request_irq(&op->dev, pdata->irq, - mpc85xx_pci_isr, IRQF_DISABLED, + mpc85xx_pci_isr, IRQF_SHARED, "[EDAC] PCI err", pci); if (res < 0) { printk(KERN_ERR @@ -312,6 +420,17 @@ int __devinit mpc85xx_pci_err_probe(struct platform_device *op) pdata->irq); } + if (pdata->pcie_flag) { + /* enable all pcie error interrupt & error detect */ + out_be32(®->pex_err_en, ~0); + out_be32(®->pex_err_disr, 0); + } else { + /* PCI master abort is expected during config cycles */ + out_be32(®->pex_err_cap_dr, PCI_ERR_CAP_DR_DIS_MST); + /* disable master abort reporting */ + out_be32(®->pex_err_en, PCI_ERR_EN_DIS_MST); + } + devres_remove_group(&op->dev, mpc85xx_pci_err_probe); edac_dbg(3, "success\n"); printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); @@ -334,10 +453,13 @@ static int mpc85xx_pci_err_remove(struct platform_device *op) edac_dbg(0, "\n"); - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, - orig_pci_err_cap_dr); + if (pdata->pcie_flag) + out_be32(&pdata->pci_reg->pex_err_disr, pdata->orig_pci_err_dr); + else + out_be32(&pdata->pci_reg->pex_err_cap_dr, + pdata->orig_pci_err_dr); - out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); + out_be32(&pdata->pci_reg->pex_err_en, pdata->orig_pci_err_en); edac_pci_del_device(pci->dev); diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h index 192c8f5..262004d 100644 --- a/drivers/edac/mpc85xx_edac.h +++ b/drivers/edac/mpc85xx_edac.h @@ -133,6 +133,9 @@ #define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \ PCI_EDE_ADDR_PERR) +#define PCI_ERR_CAP_DR_DIS_MST 0x40 +#define PCI_ERR_EN_DIS_MST (~PCI_ERR_CAP_DR_DIS_MST) +#define MPC85XX_MPIC_EIMR0 0x3910 struct mpc85xx_mc_pdata { char *name; @@ -150,8 +153,11 @@ struct mpc85xx_l2_pdata { struct mpc85xx_pci_pdata { char *name; + u8 pcie_flag; int edac_idx; - void __iomem *pci_vbase; + struct ccsr_pci *pci_reg; + u32 orig_pci_err_dr; + u32 orig_pci_err_en; int irq; };