From patchwork Thu Sep 27 01:55:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187257 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 52FCF2C0081 for ; Thu, 27 Sep 2012 12:20:45 +1000 (EST) Received: from localhost ([::1]:37107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3LP-00034k-CZ for incoming@patchwork.ozlabs.org; Wed, 26 Sep 2012 21:56:51 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3Kf-0001VG-Fx for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:56:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TH3Kc-0005zD-Lp for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:56:05 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:50416) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3Kc-0005ej-4b for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:56:02 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so2797089pbb.4 for ; Wed, 26 Sep 2012 18:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Fiq2YToeF5p1Oy0hnSEttKJcoBdSU36QHvXLnxf2h6o=; b=t2Xvqr41+YUMhO6p+iclNIESoOUZ9Xij/I89aZqUsJLZJ1V6S5vNWIHq4F0rrvQIWh MVzzjxVTypytd/5jACr+zD47xPMY9b3+IKafPWx5d7zjUJqIYOK1fonDkc+oGoiuvILD qV2nZZKjdsdyZr3GbwGbT0Xz8uu8TOBPfMyV2OikJxvSmwNSBRT/CFISZYVoAjmdjf59 7psyhGGIcXuY3nGH281VOE5nc0SGT8pFoQAgMwn0QjmgvgaPxUnK3xu/NftOszaaHqJ3 IoiX1O80xq1fAyvGEhjY8XbEXMh9Sk/l5/6mJ+OKzSOLg8bePg+e/Em5O5z+7acCFXAO DmyA== Received: by 10.68.218.101 with SMTP id pf5mr7374497pbc.60.1348710961700; Wed, 26 Sep 2012 18:56:01 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id o1sm2830071pax.21.2012.09.26.18.56.00 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 26 Sep 2012 18:56:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 26 Sep 2012 18:55:42 -0700 Message-Id: <1348710942-3040-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348710942-3040-1-git-send-email-rth@twiddle.net> References: <1348710942-3040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 12/12] tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 90a041e..72f07f9 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -124,6 +124,7 @@ static const int tcg_target_call_oarg_regs[] = { #define INSN_RS2(x) (x) #define INSN_ASI(x) ((x) << 5) +#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) @@ -185,6 +186,7 @@ static const int tcg_target_call_oarg_regs[] = { #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) +#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) @@ -572,6 +574,14 @@ static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGArg ret, | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); } +static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGArg ret, TCGArg c1, + TCGArg v1, int v1const) +{ + tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) + | (tcg_cond_to_rcond[cond] << 10) + | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); +} + static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, TCGArg c1, TCGArg c2, int c2const, TCGArg v1, int v1const) @@ -609,8 +619,16 @@ static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGArg ret, TCGArg c1, TCGArg c2, int c2const, TCGArg v1, int v1const) { - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); + /* For 64-bit signed comparisons vs zero, we can avoid the compare. + Note that the immediate range is one bit smaller, so we must check + for that as well. */ + if (c2 == 0 && !is_unsigned_cond(cond) + && (!v1const || check_fit_tl(v1, 10))) { + tcg_out_movr(s, cond, ret, c1, v1, v1const); + } else { + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); + } } #else static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond, @@ -706,9 +724,16 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret, TCGArg c1, TCGArg c2, int c2const) { - tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movi_imm13(s, ret, 0); - tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); + /* For 64-bit signed comparisons vs zero, we can avoid the compare + if the input does not overlap the output. */ + if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { + tcg_out_movi_imm13(s, ret, 0); + tcg_out_movr(s, cond, ret, c1, 1, 1); + } else { + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movi_imm13(s, ret, 0); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); + } } #else static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,