Patchwork [v3] Align PCI capabilities in pci_find_space

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Submitter mjr@cs.wisc.edu
Date Sept. 26, 2012, 3:30 p.m.
Message ID <1348673453-3248-1-git-send-email-mjr@cs.wisc.edu>
Download mbox | patch
Permalink /patch/187096/
State New
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Comments

mjr@cs.wisc.edu - Sept. 26, 2012, 3:30 p.m.
From: Matt Renzelmann <mjr@cs.wisc.edu>

The current implementation of pci_find_space does not correctly align
PCI capabilities in the PCI configuration space.  It also does not
distinguish PCI and PCI-Express devices.  This patch fixes these
issues.

Thanks to Alex Williamson for continuing feedback.

Signed-off-by: Matt Renzelmann <mjr@cs.wisc.edu>
---

In this patch, I've revised the pci_find_space function as suggested
(more-or-less).  I searched for calls to pci_add_capability, and at
this time, most rely only on capabilities that fit in the PCI config
space.  More importantly, almost all specify the capability offset
instead of relying on pci_find_space, so this change does not impact
any calls that specify an offset manually.  However, it's important to
double-check that there are no calls from PCI-E virtual devices to
pci_add_capability that both:

(a) relied on pci_find_space to find them space

(b) needed the PCI-E extended config space searched in addition to the
PCI space

as these would break with this patch. Here is the list of files that
refer to pcie_cap_init:

./hw/pcie.c
./hw/pcie.h
./hw/ioh3420.c
./hw/usb/hcd-xhci.c
./hw/xio3130_upstream.c
./hw/xio3130_downstream.c

The goal of this search was simply to find PCI-E devices--there may be
a better way.  The next list contain calls to pci_add_capability:

./hw/pci_bridge.c
./hw/shpc.c
./hw/pcie.c
./hw/kvm/pci-assign.c
./hw/msi.c
./hw/pci.c
./hw/ide/ich.c
./hw/pci.h
./hw/eepro100.c
./hw/msix.c
./hw/slotid_cap.c


 hw/pci.c |   28 +++++++++++++++++++++-------
 1 files changed, 21 insertions(+), 7 deletions(-)
Alex Williamson - Sept. 26, 2012, 4:26 p.m.
On Wed, 2012-09-26 at 10:30 -0500, mjr@cs.wisc.edu wrote:
> From: Matt Renzelmann <mjr@cs.wisc.edu>
> 
> The current implementation of pci_find_space does not correctly align
> PCI capabilities in the PCI configuration space.  It also does not
> distinguish PCI and PCI-Express devices.  This patch fixes these
> issues.
> 
> Thanks to Alex Williamson for continuing feedback.
> 
> Signed-off-by: Matt Renzelmann <mjr@cs.wisc.edu>
> ---
> 
> In this patch, I've revised the pci_find_space function as suggested
> (more-or-less).  I searched for calls to pci_add_capability, and at
> this time, most rely only on capabilities that fit in the PCI config
> space.  More importantly, almost all specify the capability offset
> instead of relying on pci_find_space, so this change does not impact
> any calls that specify an offset manually.  However, it's important to
> double-check that there are no calls from PCI-E virtual devices to
> pci_add_capability that both:
> 
> (a) relied on pci_find_space to find them space
> 
> (b) needed the PCI-E extended config space searched in addition to the
> PCI space
> 
> as these would break with this patch. Here is the list of files that
> refer to pcie_cap_init:
> 
> ./hw/pcie.c
> ./hw/pcie.h
> ./hw/ioh3420.c
> ./hw/usb/hcd-xhci.c
> ./hw/xio3130_upstream.c
> ./hw/xio3130_downstream.c
> 
> The goal of this search was simply to find PCI-E devices--there may be
> a better way.  The next list contain calls to pci_add_capability:
> 
> ./hw/pci_bridge.c
> ./hw/shpc.c
> ./hw/pcie.c
> ./hw/kvm/pci-assign.c
> ./hw/msi.c
> ./hw/pci.c
> ./hw/ide/ich.c
> ./hw/pci.h
> ./hw/eepro100.c
> ./hw/msix.c
> ./hw/slotid_cap.c
> 
> 
>  hw/pci.c |   28 +++++++++++++++++++++-------
>  1 files changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/pci.c b/hw/pci.c
> index f855cf3..2217dda 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1626,16 +1626,30 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
>      return pci_create_simple_multifunction(bus, devfn, false, name);
>  }
>  
> -static int pci_find_space(PCIDevice *pdev, uint8_t size)
> +static int pci_find_space(PCIDevice *pdev, uint8_t size, bool include_pcie)
>  {
> -    int config_size = pci_config_size(pdev);
> +    int config_size;
>      int offset = PCI_CONFIG_HEADER_SIZE;
>      int i;
> -    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
> -        if (pdev->used[i])
> -            offset = i + 1;
> -        else if (i - offset + 1 == size)
> +    uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
> +
> +    if (include_pcie) {
> +        assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
> +        config_size = PCIE_CONFIG_SPACE_SIZE;
> +    } else {
> +        config_size = PCI_CONFIG_SPACE_SIZE;
> +    }
> +
> +    /* This approach ensures the capability is dword-aligned, as
> +       required by the PCI specification */
> +    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; i += 4, dword_used++) {

I don't believe there's ever a case where a driver would want space and
not care if it's in standard or extended config space.  They'll want one
or the other.  So we'd be searching two distinct ranges.  Thanks,

Alex

> +        if (*dword_used) {
> +            offset = i + 4;
> +        } else if (i - offset + 4 >= size) {
>              return offset;
> +        }
> +    }
> +
>      return 0;
>  }
>  
> @@ -1826,7 +1840,7 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
>      int i, overlapping_cap;
>  
>      if (!offset) {
> -        offset = pci_find_space(pdev, size);
> +        offset = pci_find_space(pdev, size, false);
>          if (!offset) {
>              return -ENOSPC;
>          }
mjr@cs.wisc.edu - Sept. 26, 2012, 4:50 p.m.
> >
> >  hw/pci.c |   28 +++++++++++++++++++++-------
> >  1 files changed, 21 insertions(+), 7 deletions(-)
> >
> > diff --git a/hw/pci.c b/hw/pci.c
> > index f855cf3..2217dda 100644
> > --- a/hw/pci.c
> > +++ b/hw/pci.c
> > @@ -1626,16 +1626,30 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn,
> const char *name)
> >      return pci_create_simple_multifunction(bus, devfn, false, name);
> >  }
> >
> > -static int pci_find_space(PCIDevice *pdev, uint8_t size)
> > +static int pci_find_space(PCIDevice *pdev, uint8_t size, bool include_pcie)
> >  {
> > -    int config_size = pci_config_size(pdev);
> > +    int config_size;
> >      int offset = PCI_CONFIG_HEADER_SIZE;
> >      int i;
> > -    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
> > -        if (pdev->used[i])
> > -            offset = i + 1;
> > -        else if (i - offset + 1 == size)
> > +    uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
> > +
> > +    if (include_pcie) {
> > +        assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
> > +        config_size = PCIE_CONFIG_SPACE_SIZE;
> > +    } else {
> > +        config_size = PCI_CONFIG_SPACE_SIZE;
> > +    }
> > +
> > +    /* This approach ensures the capability is dword-aligned, as
> > +       required by the PCI specification */
> > +    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; i += 4, dword_used++)
> {
> 
> I don't believe there's ever a case where a driver would want space and
> not care if it's in standard or extended config space.  They'll want one
> or the other.  So we'd be searching two distinct ranges.  Thanks,
> 
> Alex

Ah, that makes sense, so would something like this work?  I can re-send as a patch once we've got it.

static int pci_find_space(PCIDevice *pdev, uint8_t size, bool pcie_space)
{
    int config_base;
    int config_size;
    int offset = PCI_CONFIG_HEADER_SIZE;
    int i;
    uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];

    if (pcie_space) {
        assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
        config_base = PCI_CONFIG_SPACE_SIZE;
        config_size = PCIE_CONFIG_SPACE_SIZE;
    } else {        
        config_base = PCI_CONFIG_HEADER_SIZE;
        config_size = PCI_CONFIG_SPACE_SIZE;
    }

    /* This approach ensures the capability is dword-aligned, as                                                        
       required by the PCI specification */
    for (i = config_base; i < config_size; i += 4, dword_used++) {                       
        if (*dword_used)
            offset = i + 4;
        else if (i - offset + 4 >= size)
            return offset;
    }        

    return 0;
}

Thanks for all your help with this,
Matt

> 
> > +        if (*dword_used) {
> > +            offset = i + 4;
> > +        } else if (i - offset + 4 >= size) {
> >              return offset;
> > +        }
> > +    }
> > +
> >      return 0;
> >  }
> >
> > @@ -1826,7 +1840,7 @@ int pci_add_capability(PCIDevice *pdev, uint8_t
> cap_id,
> >      int i, overlapping_cap;
> >
> >      if (!offset) {
> > -        offset = pci_find_space(pdev, size);
> > +        offset = pci_find_space(pdev, size, false);
> >          if (!offset) {
> >              return -ENOSPC;
> >          }
> 
>
Alex Williamson - Sept. 26, 2012, 4:57 p.m.
On Wed, 2012-09-26 at 11:50 -0500, Matt Renzelmann wrote:
> > >
> > >  hw/pci.c |   28 +++++++++++++++++++++-------
> > >  1 files changed, 21 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/hw/pci.c b/hw/pci.c
> > > index f855cf3..2217dda 100644
> > > --- a/hw/pci.c
> > > +++ b/hw/pci.c
> > > @@ -1626,16 +1626,30 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn,
> > const char *name)
> > >      return pci_create_simple_multifunction(bus, devfn, false, name);
> > >  }
> > >
> > > -static int pci_find_space(PCIDevice *pdev, uint8_t size)
> > > +static int pci_find_space(PCIDevice *pdev, uint8_t size, bool include_pcie)
> > >  {
> > > -    int config_size = pci_config_size(pdev);
> > > +    int config_size;
> > >      int offset = PCI_CONFIG_HEADER_SIZE;
> > >      int i;
> > > -    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
> > > -        if (pdev->used[i])
> > > -            offset = i + 1;
> > > -        else if (i - offset + 1 == size)
> > > +    uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
> > > +
> > > +    if (include_pcie) {
> > > +        assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
> > > +        config_size = PCIE_CONFIG_SPACE_SIZE;
> > > +    } else {
> > > +        config_size = PCI_CONFIG_SPACE_SIZE;
> > > +    }
> > > +
> > > +    /* This approach ensures the capability is dword-aligned, as
> > > +       required by the PCI specification */
> > > +    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; i += 4, dword_used++)
> > {
> > 
> > I don't believe there's ever a case where a driver would want space and
> > not care if it's in standard or extended config space.  They'll want one
> > or the other.  So we'd be searching two distinct ranges.  Thanks,
> > 
> > Alex
> 
> Ah, that makes sense, so would something like this work?  I can re-send as a patch once we've got it.
> 
> static int pci_find_space(PCIDevice *pdev, uint8_t size, bool pcie_space)
> {
>     int config_base;
>     int config_size;
>     int offset = PCI_CONFIG_HEADER_SIZE;
>     int i;
>     uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];

This needs to change too.

Is there a different alignment requirement for pcie?  Seems like you
might be better off creating some helper like:

pci_find_space(PCIDevice *pdev, unsigned start, unsigned size, unsigned
align)

Then a pci_find_legacy_space and pci_find_express_space could both call
into it.  Thanks,

Alex

> 
>     if (pcie_space) {
>         assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
>         config_base = PCI_CONFIG_SPACE_SIZE;
>         config_size = PCIE_CONFIG_SPACE_SIZE;
>     } else {        
>         config_base = PCI_CONFIG_HEADER_SIZE;
>         config_size = PCI_CONFIG_SPACE_SIZE;
>     }
> 
>     /* This approach ensures the capability is dword-aligned, as                                                        
>        required by the PCI specification */
>     for (i = config_base; i < config_size; i += 4, dword_used++) {                       
>         if (*dword_used)
>             offset = i + 4;
>         else if (i - offset + 4 >= size)
>             return offset;
>     }        
> 
>     return 0;
> }
> 
> Thanks for all your help with this,
> Matt
> 
> > 
> > > +        if (*dword_used) {
> > > +            offset = i + 4;
> > > +        } else if (i - offset + 4 >= size) {
> > >              return offset;
> > > +        }
> > > +    }
> > > +
> > >      return 0;
> > >  }
> > >
> > > @@ -1826,7 +1840,7 @@ int pci_add_capability(PCIDevice *pdev, uint8_t
> > cap_id,
> > >      int i, overlapping_cap;
> > >
> > >      if (!offset) {
> > > -        offset = pci_find_space(pdev, size);
> > > +        offset = pci_find_space(pdev, size, false);
> > >          if (!offset) {
> > >              return -ENOSPC;
> > >          }
> > 
> > 
> 
>
mjr@cs.wisc.edu - Sept. 26, 2012, 5:49 p.m.
> > static int pci_find_space(PCIDevice *pdev, uint8_t size, bool pcie_space)
> > {
> >     int config_base;
> >     int config_size;
> >     int offset = PCI_CONFIG_HEADER_SIZE;
> >     int i;
> >     uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
> 
> This needs to change too.
> 
> Is there a different alignment requirement for pcie?  Seems like you
> might be better off creating some helper like:

I found a copy of the PCI-E 1.0 specification -- I don't have any later copy available -- and it contains this text:

============
7.9. PCI Express Extended Capabilities

PCI Express Extended Capability registers are located in device configuration space at offsets 256 or greater ...

Each capability structure must be DWORD aligned.

...

7.9.3. PCI Express Enhanced Capability Header

Next Capability Offset – This field contains the
offset to the next PCI Express capability structure or
000h if no other items exist in the linked list of
capabilities.

...

The bottom two bits of this offset are reserved and
must be implemented as 00b although software
must mask them to allow for future uses of these
bits.
============

so, I think it's reasonable to align everything to 4-bytes all the time.  Here's another draft:


static int pci_find_space(PCIDevice *pdev, uint32_t start, uint32_t size)
{
    int offset = start;
    int i;
    uint32_t *dword_used = &pdev->used[start];

    /* This approach ensures the capability is dword-aligned, as                                                        
       required by the PCI and PCI-E specifications */
    for (i = start; i < size; i += 4, dword_used++) {
        if (*dword_used)
            offset = i + 4;
        else if (i - offset + 4 >= size)
            return offset;
    }

    return 0;
}

static int pci_find_legacy_space(PCIDevice *pdev, uint8_t size) {
    return pci_find_space(pdev, PCI_CONFIG_HEADER_SIZE, PCI_CONFIG_SPACE_SIZE);
}

static int pci_find_express_space(PCIDevice *pdev, uint16_t size) {
    assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
    return pci_find_space(pdev, PCI_CONFIG_SPACE_SIZE, PCIE_CONFIG_SPACE_SIZE);
}
Alex Williamson - Sept. 26, 2012, 5:55 p.m.
On Wed, 2012-09-26 at 12:49 -0500, Matt Renzelmann wrote:
> > > static int pci_find_space(PCIDevice *pdev, uint8_t size, bool pcie_space)
> > > {
> > >     int config_base;
> > >     int config_size;
> > >     int offset = PCI_CONFIG_HEADER_SIZE;
> > >     int i;
> > >     uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
> > 
> > This needs to change too.
> > 
> > Is there a different alignment requirement for pcie?  Seems like you
> > might be better off creating some helper like:
> 
> I found a copy of the PCI-E 1.0 specification -- I don't have any later copy available -- and it contains this text:
> 
> ============
> 7.9. PCI Express Extended Capabilities
> 
> PCI Express Extended Capability registers are located in device configuration space at offsets 256 or greater ...
> 
> Each capability structure must be DWORD aligned.
> 
> ...
> 
> 7.9.3. PCI Express Enhanced Capability Header
> 
> Next Capability Offset – This field contains the
> offset to the next PCI Express capability structure or
> 000h if no other items exist in the linked list of
> capabilities.
> 
> ...
> 
> The bottom two bits of this offset are reserved and
> must be implemented as 00b although software
> must mask them to allow for future uses of these
> bits.
> ============
> 
> so, I think it's reasonable to align everything to 4-bytes all the time.  Here's another draft:
> 
> 
> static int pci_find_space(PCIDevice *pdev, uint32_t start, uint32_t size)
> {
>     int offset = start;
>     int i;
>     uint32_t *dword_used = &pdev->used[start];
> 
>     /* This approach ensures the capability is dword-aligned, as                                                        
>        required by the PCI and PCI-E specifications */
>     for (i = start; i < size; i += 4, dword_used++) {
>         if (*dword_used)
>             offset = i + 4;
>         else if (i - offset + 4 >= size)
>             return offset;
>     }

Mismatched uses of "size" here.  We need both the end of the range to
search and the size of the sub-range we're looking for.  Maybe start,
end, and size.  Thanks,

Alex

> 
>     return 0;
> }
> 
> static int pci_find_legacy_space(PCIDevice *pdev, uint8_t size) {
>     return pci_find_space(pdev, PCI_CONFIG_HEADER_SIZE, PCI_CONFIG_SPACE_SIZE);
> }
> 
> static int pci_find_express_space(PCIDevice *pdev, uint16_t size) {
>     assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
>     return pci_find_space(pdev, PCI_CONFIG_SPACE_SIZE, PCIE_CONFIG_SPACE_SIZE);
> }
> 
>
Don Slutz - Sept. 26, 2012, 6:02 p.m.
On 09/26/12 13:55, Alex Williamson wrote:
> On Wed, 2012-09-26 at 12:49 -0500, Matt Renzelmann wrote:
>>>> static int pci_find_space(PCIDevice *pdev, uint8_t size, bool pcie_space)
>>>> {
>>>>      int config_base;
>>>>      int config_size;
>>>>      int offset = PCI_CONFIG_HEADER_SIZE;
>>>>      int i;
>>>>      uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
>>> This needs to change too.
>>>
>>> Is there a different alignment requirement for pcie?  Seems like you
>>> might be better off creating some helper like:
>> I found a copy of the PCI-E 1.0 specification -- I don't have any later copy available -- and it contains this text:
>>
>> ============
>> 7.9. PCI Express Extended Capabilities
>>
>> PCI Express Extended Capability registers are located in device configuration space at offsets 256 or greater ...
>>
>> Each capability structure must be DWORD aligned.
>>
>> ...
>>
>> 7.9.3. PCI Express Enhanced Capability Header
>>
>> Next Capability Offset – This field contains the
>> offset to the next PCI Express capability structure or
>> 000h if no other items exist in the linked list of
>> capabilities.
>>
>> ...
>>
>> The bottom two bits of this offset are reserved and
>> must be implemented as 00b although software
>> must mask them to allow for future uses of these
>> bits.
>> ============
>>
>> so, I think it's reasonable to align everything to 4-bytes all the time.  Here's another draft:
>>
>>
>> static int pci_find_space(PCIDevice *pdev, uint32_t start, uint32_t size)
>> {
>>      int offset = start;
>>      int i;
>>      uint32_t *dword_used = &pdev->used[start];
>>
>>      /* This approach ensures the capability is dword-aligned, as
>>         required by the PCI and PCI-E specifications */
>>      for (i = start; i < size; i += 4, dword_used++) {
>>          if (*dword_used)
I would think that dword_used needs to be based on i not start.
>>              offset = i + 4;
>>          else if (i - offset + 4 >= size)
>>              return offset;
>>      }
> Mismatched uses of "size" here.  We need both the end of the range to
> search and the size of the sub-range we're looking for.  Maybe start,
> end, and size.  Thanks,
>
> Alex
>
>>      return 0;
>> }
>>
>> static int pci_find_legacy_space(PCIDevice *pdev, uint8_t size) {
>>      return pci_find_space(pdev, PCI_CONFIG_HEADER_SIZE, PCI_CONFIG_SPACE_SIZE);
>> }
>>
>> static int pci_find_express_space(PCIDevice *pdev, uint16_t size) {
>>      assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
>>      return pci_find_space(pdev, PCI_CONFIG_SPACE_SIZE, PCIE_CONFIG_SPACE_SIZE);
>> }
>>
>>
>
>
>
    -Don Slutz
Don Slutz - Sept. 26, 2012, 6:04 p.m.
On 09/26/12 14:02, Don Slutz wrote:
> On 09/26/12 13:55, Alex Williamson wrote:
>> On Wed, 2012-09-26 at 12:49 -0500, Matt Renzelmann wrote:
>>>>> static int pci_find_space(PCIDevice *pdev, uint8_t size, bool 
>>>>> pcie_space)
>>>>> {
>>>>>      int config_base;
>>>>>      int config_size;
>>>>>      int offset = PCI_CONFIG_HEADER_SIZE;
>>>>>      int i;
>>>>>      uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
>>>> This needs to change too.
>>>>
>>>> Is there a different alignment requirement for pcie?  Seems like you
>>>> might be better off creating some helper like:
>>> I found a copy of the PCI-E 1.0 specification -- I don't have any 
>>> later copy available -- and it contains this text:
>>>
>>> ============
>>> 7.9. PCI Express Extended Capabilities
>>>
>>> PCI Express Extended Capability registers are located in device 
>>> configuration space at offsets 256 or greater ...
>>>
>>> Each capability structure must be DWORD aligned.
>>>
>>> ...
>>>
>>> 7.9.3. PCI Express Enhanced Capability Header
>>>
>>> Next Capability Offset – This field contains the
>>> offset to the next PCI Express capability structure or
>>> 000h if no other items exist in the linked list of
>>> capabilities.
>>>
>>> ...
>>>
>>> The bottom two bits of this offset are reserved and
>>> must be implemented as 00b although software
>>> must mask them to allow for future uses of these
>>> bits.
>>> ============
>>>
>>> so, I think it's reasonable to align everything to 4-bytes all the 
>>> time.  Here's another draft:
>>>
>>>
>>> static int pci_find_space(PCIDevice *pdev, uint32_t start, uint32_t 
>>> size)
>>> {
>>>      int offset = start;
>>>      int i;
>>>      uint32_t *dword_used = &pdev->used[start];
>>>
>>>      /* This approach ensures the capability is dword-aligned, as
>>>         required by the PCI and PCI-E specifications */
>>>      for (i = start; i < size; i += 4, dword_used++) {
Opps, I missed the dword_used++

Forget this comment...

>>>          if (*dword_used)
> I would think that dword_used needs to be based on i not start.
>>>              offset = i + 4;
>>>          else if (i - offset + 4 >= size)
>>>              return offset;
>>>      }
>> Mismatched uses of "size" here.  We need both the end of the range to
>> search and the size of the sub-range we're looking for.  Maybe start,
>> end, and size.  Thanks,
>>
>> Alex
>>
>>>      return 0;
>>> }
>>>
>>> static int pci_find_legacy_space(PCIDevice *pdev, uint8_t size) {
>>>      return pci_find_space(pdev, PCI_CONFIG_HEADER_SIZE, 
>>> PCI_CONFIG_SPACE_SIZE);
>>> }
>>>
>>> static int pci_find_express_space(PCIDevice *pdev, uint16_t size) {
>>>      assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
>>>      return pci_find_space(pdev, PCI_CONFIG_SPACE_SIZE, 
>>> PCIE_CONFIG_SPACE_SIZE);
>>> }
>>>
>>>
>>
>>
>>
>    -Don Slutz
>
   -Don Slutz
mjr@cs.wisc.edu - Sept. 26, 2012, 6:05 p.m.
> 
> Mismatched uses of "size" here.  We need both the end of the range to
> search and the size of the sub-range we're looking for.  Maybe start,
> end, and size.  Thanks,
> 

Ah of course, how's this:

static int pci_find_space(PCIDevice *pdev, uint32_t start,
                          uint32_t end, uint32_t size)
{
    int offset = start;
    int i;
    uint32_t *dword_used = &pdev->used[start];

    /* This approach ensures the capability is dword-aligned, as 
       required by the PCI and PCI-E specifications */
    for (i = start; i < end; i += 4, dword_used++) { 
        if (*dword_used)
            offset = i + 4;
        else if (i - offset + 4 >= size)
            return offset;
    }

    return 0;
}

static int pci_find_legacy_space(PCIDevice *pdev, uint8_t size) {
    return pci_find_space(pdev, PCI_CONFIG_HEADER_SIZE,
                          PCI_CONFIG_SPACE_SIZE, size);
}

static int pci_find_express_space(PCIDevice *pdev, uint16_t size) {
    assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
    return pci_find_space(pdev, PCI_CONFIG_SPACE_SIZE,
                          PCIE_CONFIG_SPACE_SIZE, size);
}
Alex Williamson - Sept. 26, 2012, 6:15 p.m.
On Wed, 2012-09-26 at 13:05 -0500, Matt Renzelmann wrote:
> > 
> > Mismatched uses of "size" here.  We need both the end of the range to
> > search and the size of the sub-range we're looking for.  Maybe start,
> > end, and size.  Thanks,
> > 
> 
> Ah of course, how's this:
> 
> static int pci_find_space(PCIDevice *pdev, uint32_t start,
>                           uint32_t end, uint32_t size)
> {
>     int offset = start;
>     int i;
>     uint32_t *dword_used = &pdev->used[start];
> 
>     /* This approach ensures the capability is dword-aligned, as 
>        required by the PCI and PCI-E specifications */
>     for (i = start; i < end; i += 4, dword_used++) { 
>         if (*dword_used)
>             offset = i + 4;
>         else if (i - offset + 4 >= size)
>             return offset;
>     }
> 
>     return 0;
> }

Looks reasonable to me

> static int pci_find_legacy_space(PCIDevice *pdev, uint8_t size) {
>     return pci_find_space(pdev, PCI_CONFIG_HEADER_SIZE,
>                           PCI_CONFIG_SPACE_SIZE, size);
> }
> 
> static int pci_find_express_space(PCIDevice *pdev, uint16_t size) {
>     assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);

This could be done generically in pci_find_space

assert(pci_config_size(pdev) >= end)

You could also add an alignment check

assert(!(start & 0x3))

Thanks,

Alex

>     return pci_find_space(pdev, PCI_CONFIG_SPACE_SIZE,
>                           PCIE_CONFIG_SPACE_SIZE, size);
> }
>

Patch

diff --git a/hw/pci.c b/hw/pci.c
index f855cf3..2217dda 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1626,16 +1626,30 @@  PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
     return pci_create_simple_multifunction(bus, devfn, false, name);
 }
 
-static int pci_find_space(PCIDevice *pdev, uint8_t size)
+static int pci_find_space(PCIDevice *pdev, uint8_t size, bool include_pcie)
 {
-    int config_size = pci_config_size(pdev);
+    int config_size;
     int offset = PCI_CONFIG_HEADER_SIZE;
     int i;
-    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
-        if (pdev->used[i])
-            offset = i + 1;
-        else if (i - offset + 1 == size)
+    uint32_t *dword_used = &pdev->used[PCI_CONFIG_HEADER_SIZE];
+
+    if (include_pcie) {
+        assert (pci_config_size(pdev) >= PCIE_CONFIG_SPACE_SIZE);
+        config_size = PCIE_CONFIG_SPACE_SIZE;
+    } else {
+        config_size = PCI_CONFIG_SPACE_SIZE;
+    }
+
+    /* This approach ensures the capability is dword-aligned, as
+       required by the PCI specification */
+    for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; i += 4, dword_used++) {
+        if (*dword_used) {
+            offset = i + 4;
+        } else if (i - offset + 4 >= size) {
             return offset;
+        }
+    }
+
     return 0;
 }
 
@@ -1826,7 +1840,7 @@  int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
     int i, overlapping_cap;
 
     if (!offset) {
-        offset = pci_find_space(pdev, size);
+        offset = pci_find_space(pdev, size, false);
         if (!offset) {
             return -ENOSPC;
         }