Patchwork [AArch64] Tighten predicate for CMP pattern.

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Submitter Marcus Shawcroft
Date Sept. 26, 2012, 8:43 a.m.
Message ID <5062C03F.5030209@arm.com>
Download mbox | patch
Permalink /patch/186993/
State New
Headers show

Comments

Marcus Shawcroft - Sept. 26, 2012, 8:43 a.m.
On 10/09/12 16:11, Tejas Belagod wrote:
> Hi,
>
> This patch tightens the predicate for the CMP pattern. It makes it restrictive
> to accept reg or zero as prescribed by the architecture.
>
> Regression-tested on aarch64-none-elf. OK for aarch64-branch?
>
> Thanks,
> Tejas Belagod
> ARM.
>
> PS: This patch applies over vldn-vstn.txt sent out earlier.
>
> Changelog:
>
> 2012-09-10  Tejas Belagod<tejas.belagod@arm.com>
>
> gcc/
> 	* config/aarch64/aarch64-simd.md (aarch64_cm<cmp><mode>): Tighten
> 	predicate for operand 2 of the compare pattern to accept register
> 	or zero.
> 	* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New.

Tejas

This patch duplicated the definition of aarch64_simd_reg_or_zero 
introduced by the earlier vld234 patch.  I've committed the attached fix 
to aarch64-branch and aarch64-4.7-branch

Cheers
/Marcus


2012-09-26  Marcus Shawcroft <marcus.shawcroft@arm.com>

	* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): Remove
	duplicate.

Patch

Index: gcc/config/aarch64/predicates.md
===================================================================
--- gcc/config/aarch64/predicates.md	(revision 191754)
+++ gcc/config/aarch64/predicates.md	(working copy)
@@ -295,9 +295,3 @@ 
 {
   return aarch64_simd_imm_zero_p (op, mode);
 })
-
-(define_predicate "aarch64_simd_reg_or_zero"
-  (and (match_code "reg,subreg,const_int,const_vector")
-       (ior (match_operand 0 "register_operand")
-	    (ior (match_test "op == const0_rtx")
-	    	  (match_test "aarch64_simd_imm_zero_p (op, mode)")))))