diff mbox

rs6000: Fix ne0 patterns (PR51274)

Message ID 20e6bad3776b5157e514b17dfe8bf560b6ffdb79.1348547367.git.segher@kernel.crashing.org
State New
Headers show

Commit Message

Segher Boessenkool Sept. 25, 2012, 4:44 a.m. UTC 
The current patterns will never match.  Fix that.  Also, merge the
SI and DI variants of each.  Also, remove an unnecessary earlyclobber.
And add a pattern for what combine considers the canonical form of
one of these patterns.

Bootstrapped and regression checked on powerpc64-linux.  Also tested
all these patterns manually, -m32 and -m64 and -m32 -mpowerpc64,
-misel and -mno-isel.

Okay to apply?


Segher


2012-09-24  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/
	PR target/51274
	* config/rs6000/rs6000.md (ne0si): Remove unnecessary
	earlyclobber.  Merge with...
	(ne0di): ... to...
	(ne0_<mode>): New.
	(plus_ne0si): Merge with...
	(plus_ne0di): ... to...
	(plus_ne0_<mode>): New.
	(compare_plus_ne0si): Merge with...
	(compare_plus_ne0di)... to...
	(compare_plus_ne0_<mode>): New.
	(compare_plus_ne0_<mode>_1): New.
	(plus_ne0si_compare): Merge with...
	(plus_ne0di_compare)... to...
	(plus_ne0_<mode>_compare): New.


---
 gcc/config/rs6000/rs6000.md |  223 +++++++++++++++----------------------------
 1 files changed, 75 insertions(+), 148 deletions(-)

Comments

Segher Boessenkool Sept. 25, 2012, 8:03 a.m. UTC | #1 
> 	PR target/51274

Also:
	PR target/53087
David Edelsohn Sept. 25, 2012, 1:32 p.m. UTC | #2 
On Tue, Sep 25, 2012 at 12:44 AM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> The current patterns will never match.  Fix that.  Also, merge the
> SI and DI variants of each.  Also, remove an unnecessary earlyclobber.
> And add a pattern for what combine considers the canonical form of
> one of these patterns.
>
> Bootstrapped and regression checked on powerpc64-linux.  Also tested
> all these patterns manually, -m32 and -m64 and -m32 -mpowerpc64,
> -misel and -mno-isel.
>
> Okay to apply?
>
>
> Segher
>
>
> 2012-09-24  Segher Boessenkool  <segher@kernel.crashing.org>
>
> gcc/
>         PR target/51274
>         * config/rs6000/rs6000.md (ne0si): Remove unnecessary
>         earlyclobber.  Merge with...
>         (ne0di): ... to...
>         (ne0_<mode>): New.
>         (plus_ne0si): Merge with...
>         (plus_ne0di): ... to...
>         (plus_ne0_<mode>): New.
>         (compare_plus_ne0si): Merge with...
>         (compare_plus_ne0di)... to...
>         (compare_plus_ne0_<mode>): New.
>         (compare_plus_ne0_<mode>_1): New.
>         (plus_ne0si_compare): Merge with...
>         (plus_ne0di_compare)... to...
>         (plus_ne0_<mode>_compare): New.

This is okay, but can you also add a target testcase to check that the
correct assembly instructions are generated so that we can try to
ensure this does not regress again?

Thanks, David
Segher Boessenkool Sept. 25, 2012, 1:40 p.m. UTC | #3 
> This is okay, but can you also add a target testcase to check that the
> correct assembly instructions are generated so that we can try to
> ensure this does not regress again?

This won't regress in this way again, because now the pattern is a
single RTL op.  But yes, target tests for this kind of thing would
be quite useful.

However, I'm going to overhaul the whole SCC thing, so I'd rather
add tests for everything at once.  OTOH, it's a good exercise I
suppose...  Your choice :-)


Segher
Michael Meissner Sept. 25, 2012, 4:14 p.m. UTC | #4 
On Tue, Sep 25, 2012 at 03:40:10PM +0200, Segher Boessenkool wrote:
> >This is okay, but can you also add a target testcase to check that the
> >correct assembly instructions are generated so that we can try to
> >ensure this does not regress again?
> 
> This won't regress in this way again, because now the pattern is a
> single RTL op.  But yes, target tests for this kind of thing would
> be quite useful.
> 
> However, I'm going to overhaul the whole SCC thing, so I'd rather
> add tests for everything at once.  OTOH, it's a good exercise I
> suppose...  Your choice :-)

Yes, I had probably fixed that regression 2-3 times while I was rewriting the
SCC stuff, but since I never could get any improvements without regressions, I
put it on the back burner to get to more stuff.

If you want, I can share what I had.
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9f96270..4265cb6 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11970,64 +11970,36 @@  (define_insn_and_split "*neg_eq<mode>"
       operands[3] = operands[1];
   })
 
-;; Simplify (ne X (const_int 0)) on the PowerPC.  No need to on the Power,
-;; since it nabs/sr is just as fast.
-(define_insn "*ne0si"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
-	(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
-		     (const_int 31)))
-   (clobber (match_scratch:SI 2 "=&r"))]
-  "TARGET_32BIT && !TARGET_ISEL"
-  "addic %2,%1,-1\;subfe %0,%2,%1"
-  [(set_attr "type" "two")
-   (set_attr "length" "8")])
-
-(define_insn "*ne0di"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
-		     (const_int 63)))
-   (clobber (match_scratch:DI 2 "=&r"))]
-  "TARGET_64BIT"
+(define_insn "*ne0_<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(ne:P (match_operand:P 1 "gpc_reg_operand" "r")
+	      (const_int 0)))
+   (clobber (match_scratch:P 2 "=&r"))]
+  "!(TARGET_32BIT && TARGET_ISEL)"
   "addic %2,%1,-1\;subfe %0,%2,%1"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-;; This is what (plus (ne X (const_int 0)) Y) looks like.
-(define_insn "*plus_ne0si"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(plus:SI (lshiftrt:SI
-		  (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
-		  (const_int 31))
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&r"))]
-  "TARGET_32BIT"
-  "addic %3,%1,-1\;addze %0,%2"
-  [(set_attr "type" "two")
-   (set_attr "length" "8")])
-
-(define_insn "*plus_ne0di"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(plus:DI (lshiftrt:DI
-		  (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
-		  (const_int 63))
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:DI 3 "=&r"))]
-  "TARGET_64BIT"
+(define_insn "*plus_ne0_<mode>"
+  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
+	(plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
+		      (const_int 0))
+		(match_operand:P 2 "gpc_reg_operand" "r")))
+   (clobber (match_scratch:P 3 "=&r"))]
+  ""
   "addic %3,%1,-1\;addze %0,%2"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
-(define_insn "*compare_plus_ne0si"
+(define_insn "*compare_plus_ne0_<mode>"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 31))
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))
-   (clobber (match_scratch:SI 4 "=X,&r"))]
-  "TARGET_32BIT"
+	(compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+				  (const_int 0))
+			    (match_operand:P 2 "gpc_reg_operand" "r,r"))
+		    (const_int 0)))
+   (clobber (match_scratch:P 3 "=&r,&r"))
+   (clobber (match_scratch:P 4 "=X,&r"))]
+  ""
   "@
    addic %3,%1,-1\;addze. %3,%2
    #"
@@ -12035,36 +12007,32 @@  (define_insn "*compare_plus_ne0si"
    (set_attr "length" "8,12")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
-		   (const_int 31))
-		  (match_operand:SI 2 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_32BIT && reload_completed"
+  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+	(compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "r,r")
+			  (const_int 0))
+		    (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
+   (clobber (match_scratch:P 3 ""))
+   (clobber (match_scratch:P 4 ""))]
+  "reload_completed"
   [(parallel [(set (match_dup 3)
-		   (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
-					 (const_int 31))
-			    (match_dup 2)))
+		   (plus:P (ne:P (match_dup 1)
+				 (const_int 0))
+			   (match_dup 2)))
               (clobber (match_dup 4))])
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
 		    (const_int 0)))]
   "")
 
-(define_insn "*compare_plus_ne0di"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:DI (lshiftrt:DI
-		   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 63))
-		  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (clobber (match_scratch:DI 3 "=&r,&r"))]
-  "TARGET_64BIT"
+; For combine.
+(define_insn "*compare_plus_ne0_<mode>_1"
+  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
+	(compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+			    (const_int 0))
+		      (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
+   (clobber (match_scratch:P 3 "=&r,&r"))
+   (clobber (match_scratch:P 4 "=X,&r"))]
+  ""
   "@
    addic %3,%1,-1\;addze. %3,%2
    #"
@@ -12072,78 +12040,36 @@  (define_insn "*compare_plus_ne0di"
    (set_attr "length" "8,12")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC
-	 (plus:DI (lshiftrt:DI
-		   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
-		   (const_int 63))
-		  (match_operand:DI 2 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_64BIT && reload_completed"
-  [(set (match_dup 3)
-	(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
-		   (const_int 63))
-		  (match_dup 2)))
+  [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
+	(compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "r,r")
+			    (const_int 0))
+		      (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
+   (clobber (match_scratch:P 3 ""))
+   (clobber (match_scratch:P 4 ""))]
+  "reload_completed"
+  [(parallel [(set (match_dup 3)
+		   (plus:P (ne:P (match_dup 1)
+				 (const_int 0))
+			   (match_dup 2)))
+              (clobber (match_dup 4))])
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
 		    (const_int 0)))]
   "")
 
-(define_insn "*plus_ne0si_compare"
+(define_insn "*plus_ne0_<mode>_compare"
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
-	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 31))
-		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+	 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+		       (const_int 0))
+		 (match_operand:P 2 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  "TARGET_32BIT"
-  "@
-   addic %3,%1,-1\;addze. %0,%2
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
-	(compare:CC
-	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
-		   (const_int 31))
-		  (match_operand:SI 2 "gpc_reg_operand" ""))
-	 (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
-		 (match_dup 2)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_32BIT && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
-		 (match_dup 2)))
-   (clobber (match_dup 3))])
-   (set (match_dup 4)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*plus_ne0di_compare"
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
-	(compare:CC
-	 (plus:DI (lshiftrt:DI
-		   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
-		   (const_int 63))
-		  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
-	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
-		 (match_dup 2)))
-   (clobber (match_scratch:DI 3 "=&r,&r"))]
-  "TARGET_64BIT"
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(plus:P (ne:P (match_dup 1)
+		      (const_int 0))
+		(match_dup 2)))
+   (clobber (match_scratch:P 3 "=&r,&r"))]
+  ""
   "@
    addic %3,%1,-1\;addze. %0,%2
    #"
@@ -12153,20 +12079,21 @@  (define_insn "*plus_ne0di_compare"
 (define_split
   [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
 	(compare:CC
-	 (plus:DI (lshiftrt:DI
-		   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
-		   (const_int 63))
-		  (match_operand:DI 2 "gpc_reg_operand" ""))
+	 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
+		       (const_int 0))
+		 (match_operand:P 2 "gpc_reg_operand" ""))
 	 (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
-		 (match_dup 2)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_64BIT && reload_completed"
+   (set (match_operand:P 0 "gpc_reg_operand" "")
+	(plus:P (ne:P (match_dup 1)
+		      (const_int 0))
+		(match_dup 2)))
+   (clobber (match_scratch:P 3 ""))]
+  "reload_completed"
   [(parallel [(set (match_dup 0)
-	(plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
-		 (match_dup 2)))
-   (clobber (match_dup 3))])
+		   (plus:P (ne:P (match_dup 1)
+				 (const_int 0))
+			   (match_dup 2)))
+	      (clobber (match_dup 3))])
    (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]