From patchwork Mon Sep 24 15:29:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_Bie=C3=9Fmann?= X-Patchwork-Id: 186465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E67342C0082 for ; Tue, 25 Sep 2012 01:31:01 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TGAbU-0003Tp-Fd; Mon, 24 Sep 2012 15:29:48 +0000 Received: from moutng.kundenserver.de ([212.227.17.8]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TGAbP-0003TR-Ss for linux-mtd@lists.infradead.org; Mon, 24 Sep 2012 15:29:44 +0000 Received: from corscience.de (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0MHKKd-1TCXxr2ZZz-00DxLA; Mon, 24 Sep 2012 17:29:36 +0200 Received: from [192.168.102.103] (azuregos.2og.er.corscience.de [192.168.102.103]) by corscience.de (Postfix) with ESMTP id 3294E51CE2; Mon, 24 Sep 2012 17:29:36 +0200 (CEST) Message-ID: <50607C5F.3000501@corscience.de> Date: Mon, 24 Sep 2012 17:29:35 +0200 From: =?ISO-8859-1?Q?Andreas_Bie=DFmann?= Organization: Corscience GmbH & Co. KG User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:15.0) Gecko/20120907 Thunderbird/15.0.1 MIME-Version: 1.0 To: Peter Barada Subject: Re: Per-partition NAND ECC? References: <50607688.6090601@gmail.com> In-Reply-To: <50607688.6090601@gmail.com> X-Enigmail-Version: 1.4.4 X-Provags-ID: V02:K0:KhEusqYZDk5FFCftY3Cb29XVJRYlA1jXuexcIEmvvqj TvNKRLjhOFR1qsbaGxvT/luxshvOg0AkD93uB66C7ItlCItpNw yalTgmI9y8KVkTK2b3z1DTtUGJYcrOTc3mZvQfbTJ6UNLuHO5J rN7T7b4tJyk5jSiLwnMFJfMDzW+rzWm1LDBW7ewwvifcVtw9sc c2zIkCCsqkY64DbWifnAoQds93OfVe6hgWLRq8RhutYhe7TGuB NOIUNGyMoohsFa2pIwBRB8ir3HZEkup+BKkpdyHUJe0k6FwGaY mGzXXMDcpWepSoAG+USZ/hEy/D5ug2evw8dtNA1hfMgyIk/xUW yTuIUvit8BAnlowkYwtk= X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.17.8 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "linux-mtd@lists.infradead.org" X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org On 24.09.2012 17:04, Peter Barada wrote: > On the OMAP3 parts the bootrom has a hard requirement of using 1-bit > Hamming ECC to read the 2nd stage bootloader(x-loader / SPL) out of the > first four blocks of NAND. The Micron MT29C4G48MAZAPAKQ5 PoP part we're > using requires 4-bit ECC for all the other NAND blocks to maintain an > acceptable UBER. > > Currently this wasn't a problem since I could use u-boot to update the > 2nd stage bootloader. I now have a need to be able to update the 2nd > stage bootloader from Linux only so I need the ability to write/read > pages in a NAND partition with a different ECC method than that > specified over the device. I think it would be more elegant to solve > this by allowing partition entry/mtdparts to specify its ECC > methodology, track that as part of the MTD device down into the nand > driver, and switch ECC methods/entrypoints as it changes. > > Does anyone have suggestions on how to best approach this? We have the same problem here. We modified the omap2 nand driver to have the ecc type configurable as module parameter. In our upgrade scenario we can unload the omap2 module cause we are running from initrd and so we can switch the ecc type by module parameter quite easy. Your suggestion to switch ecc per mtd sound way better, but sorry I have currently no insights how to implement this in a proper way. I don't know if there is an generic way to bind the ecc information to an mtd. You can find our solution attached (is added by c'n'p thus may have wrong line wraps). If anybody is interested in this solution, I can provide a proper patch. And beware, you will need [1] and [2] for safe unloading of omap2 nand driver. Best regards Andreas Bießmann [1] http://git.infradead.org/users/dedekind/l2-mtd.git/commit/44552d26885a25b423c6606fd5f203aa95dc953f [2] http://git.infradead.org/users/dedekind/l2-mtd.git/commit/14178ea6dd8a6575616ce439389a8dd45e149aa8 --- static struct nand_ecclayout omap_oobinfo; /* Define some generic bad / good block scan pattern which are used @@ -931,6 +935,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) struct omap_nand_platform_data *pdata; int err; int i, offset; + enum omap_ecc ecc_opt; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1052,10 +1057,13 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.verify_buf = omap_verify_buf; /* selsect the ecc type */ - if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) + ecc_opt = (eccmode == -1) ? pdata->ecc_opt : eccmode; + dev_info(&pdev->dev, "Using ECC mode %d\n", ecc_opt); + + if (ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) info->nand.ecc.mode = NAND_ECC_SOFT; - else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || - (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { + else if ((ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || + (ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { info->nand.ecc.bytes = 3; info->nand.ecc.size = 512; info->nand.ecc.strength = 1; @@ -1077,7 +1085,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } /* rom code layout */ - if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { + if (ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { if (info->nand.options & NAND_BUSWIDTH_16) offset = 2; diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index c2b0bba..7f2ca2e 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -95,6 +95,10 @@ #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) +static int eccmode = -1; +module_param(eccmode, int, 0); +MODULE_PARM_DESC(eccmode, "ECC mode (-1=platform data, 0=sw, 1=hw, 2=hwrom)"); + /* oob info generated runtime depending on ecc algorithm and layout selected */