From patchwork Sat Sep 22 11:45:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 186126 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3136B2C0095 for ; Sat, 22 Sep 2012 21:46:24 +1000 (EST) Received: from localhost ([::1]:58947 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFOAA-0003aO-PD for incoming@patchwork.ozlabs.org; Sat, 22 Sep 2012 07:46:22 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47248) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFOA3-0003a2-NB for qemu-devel@nongnu.org; Sat, 22 Sep 2012 07:46:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFOA2-0004zH-OR for qemu-devel@nongnu.org; Sat, 22 Sep 2012 07:46:15 -0400 Received: from mout.web.de ([212.227.15.3]:64016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFOA2-0004z9-FK for qemu-devel@nongnu.org; Sat, 22 Sep 2012 07:46:14 -0400 Received: from localhost.localdomain ([62.157.73.36]) by smtp.web.de (mrweb103) with ESMTPSA (Nemesis) id 0M09hY-1TTclA4Bum-00ubz8; Sat, 22 Sep 2012 13:46:10 +0200 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sat, 22 Sep 2012 13:45:54 +0200 Message-Id: <1348314355-10992-2-git-send-email-andreas.faerber@web.de> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1348314355-10992-1-git-send-email-andreas.faerber@web.de> References: <505C9E59.2040308@suse.de> <1348314355-10992-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 X-Provags-ID: V02:K0:CU9YQhCmHp+dUCitCCEVtki55F3RQCcNk7BfVvmZlzq tcLtKO1e1DvAFhNsgtqSBr/FCjno2pu0GQVVcn1dP0AfgGNAqx Y4oQWy5VDONc11pKbz1KDPluHv4xi7WNtMoGGBelZt+oV804cr cTBa6S8plq+9/VbR6o7yTzbVh4fYIjPQWGdxnNk5xKe9xOKvLo 8/pyoXFyhtwkFgL6B2PBQ== X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 212.227.15.3 Cc: giancarlo.asnaghi@st.com, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Peter Maydell Subject: [Qemu-devel] [RFC v2 2/2] target-arm: Add support for Cortex-R4F X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org With QOM ARMCPU we can now distinguish between -cpu cortex-r4 and -cpu cortex-r4f despite identical MIDR. Signed-off-by: Andreas Färber --- target-arm/cpu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 Datei geändert, 47 Zeilen hinzugefügt(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 6726498..e176559 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -405,6 +405,52 @@ static void cortex_r4_initfn(Object *obj) cpu->id_isar5 = 0x0; } +static const struct { + uint8_t r; + uint8_t p; + uint8_t value; +} cortexr4_fpsid_revs[] = { + { 1, 0, 0x3 }, + { 1, 1, 0x4 }, + { 1, 2, 0x6 }, + { 1, 3, 0x7 }, + { 1, 4, 0x8 }, + {} +}; + +static void cortex_r4f_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + /* Cortex-R4F = Cortex-R4 + FPU */ + cortex_r4_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_VFP3); + /* TODO VFPv3-D16 */ + { + /* PMM didn't like this dynamic revision lookup... */ + /* TODO: maybe weave cross-checks into QOM properties instead? */ + uint8_t r = (cpu->midr >> 20) & 0xf; + uint8_t p = cpu->midr & 0xf; + uint8_t rev = 0; + int i; + /* Calculate FPSID value matching to MIDR */ + for (i = 0; cortexr4_fpsid_revs[i].r != 0; i++) { + if (cortexr4_fpsid_revs[i].r == r && + cortexr4_fpsid_revs[i].p == p) { + rev = cortexr4_fpsid_revs[i].value; + break; + } + } + if (rev == 0) { + cpu_abort(&cpu->env, + "Cortex-R4F r%" PRIu8 "p%" PRIu8 " unsupported", + r, p); + } + cpu->reset_fpsid = 0x41023140 | (rev & 0xf); + } +} + static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -761,6 +807,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m3", .initfn = cortex_m3_initfn }, { .name = "cortex-r4", .initfn = cortex_r4_initfn }, + { .name = "cortex-r4f", .initfn = cortex_r4f_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn },