diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2b96cdc..7f3b7c1 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
 COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
 COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+COBJS-$(CONFIG_MRVL_MMC) += mrvl_mmc.o
 COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
 COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
 COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
diff --git a/drivers/mmc/mrvl_mmc.c b/drivers/mmc/mrvl_mmc.c
new file mode 100644
index 0000000..8127961
--- /dev/null
+++ b/drivers/mmc/mrvl_mmc.c
@@ -0,0 +1,277 @@
+/*
+ * Driver for Marvell SDIO/MMC controller
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lior Amsalem <alior@marvell.com>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+#include <mmc.h>
+
+#include <mrvl_mmc.h>
+#define MRVL_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+
+
+static int mrvl_mmc_setup_data(struct mmc_data *data)
+{
+	if (data->flags & MMC_DATA_READ) {
+		SDIO_REG_WRITE16(SDIO_SYS_ADDR_LOW,((ulong)(data->dest)) & 0xffff);
+		SDIO_REG_WRITE16(SDIO_SYS_ADDR_HI,(((ulong)data->dest) >> 16) & 0xffff);
+	} else {
+		SDIO_REG_WRITE16(SDIO_SYS_ADDR_LOW,((ulong)(data->src)) & 0xffff);
+		SDIO_REG_WRITE16(SDIO_SYS_ADDR_HI,(((ulong)data->src) >> 16) & 0xffff);
+	}
+
+	SDIO_REG_WRITE16(SDIO_BLK_SIZE, data->blocksize);
+	SDIO_REG_WRITE16(SDIO_BLK_COUNT, data->blocks);
+
+	return 0;
+}
+
+static int mrvl_mmc_send_cmd (struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	int	timeout = 10;
+	ushort waittype = 0;
+	int err = 0 ;
+	ushort response[8], resp_indx = 0;
+	ushort resptype = 0;
+	ushort xfertype = 0;
+
+#ifdef DEBUG
+	printf("cmd [0x%x] resp_type[0x%x] arg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
+#endif
+
+	/* clear status */
+	SDIO_REG_WRITE16(SDIO_NOR_INTR_STATUS, 0xffff);
+	SDIO_REG_WRITE16(SDIO_ERR_INTR_STATUS, 0xffff);
+
+	/* Checking if card is busy */
+	while ((SDIO_REG_READ16(SDIO_PRESENT_STATE0) & CARD_BUSY)) {
+		if (timeout == 0) {
+			printf("MRVL MMC: card busy!\n");
+			return -1;
+		}
+		timeout--;
+		udelay(1000);
+	}
+	
+	/* Set up for a data transfer if we have one */
+	if (data) {
+		int err;
+		err = mrvl_mmc_setup_data(data);
+		if(err)
+			return err;
+	}
+
+	/* Analyzing resptype/xfertype/waittype for the command */
+	if (cmd->resp_type & MMC_RSP_BUSY)
+		resptype |= SDIO_CMD_RSP_48BUSY;
+	else if (cmd->resp_type & MMC_RSP_136)
+		resptype |= SDIO_CMD_RSP_136;
+	else if (cmd->resp_type & MMC_RSP_PRESENT)
+		resptype |= SDIO_CMD_RSP_48;
+	else
+		resptype |= SDIO_CMD_RSP_NONE;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		resptype |= SDIO_CMD_CHECK_CMDCRC;
+
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		resptype |= SDIO_CMD_INDX_CHECK;
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		resptype |= SDIO_UNEXPECTED_RESP;
+		waittype |= SDIO_NOR_UNEXP_RSP;
+	}
+
+	if (data) {
+		resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
+		xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
+		if (data->flags & MMC_DATA_READ) {
+			xfertype |= SDIO_XFER_MODE_TO_HOST;
+			waittype = SDIO_NOR_DMA_INI;
+		} else
+			waittype |= SDIO_NOR_XFER_DONE;
+	} else {
+		waittype |= SDIO_NOR_CMD_DONE;
+	}
+
+	/* Setting cmd arguments */
+	SDIO_REG_WRITE16(SDIO_ARG_LOW, (ushort)(cmd->cmdarg & 0xffff));
+	SDIO_REG_WRITE16(SDIO_ARG_HI,  (ushort)(cmd->cmdarg >> 16) );
+
+	/* Setting Xfer mode */
+	SDIO_REG_WRITE16(SDIO_XFER_MODE, xfertype);
+
+	/* Sending command */
+	SDIO_REG_WRITE16(SDIO_CMD, MRVL_MMC_MAKE_CMD(cmd->cmdidx, resptype));
+
+	/* Waiting for completion */
+	timeout = 1000000;
+
+	while (!((SDIO_REG_READ16(SDIO_NOR_INTR_STATUS)) & waittype)) {
+		udelay(1);
+		if (SDIO_REG_READ16(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
+#ifdef DEBUG
+			printf("mrvl_mmc_send_cmd: error! cmd : %d, err reg: %04x\n", cmd->cmdidx, SDIO_REG_READ16(SDIO_ERR_INTR_STATUS));
+#endif
+			if (SDIO_REG_READ16(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+				return TIMEOUT;
+			return COMM_ERR;
+		}
+		timeout--;
+		if (timeout <= 0) {
+			printf("MRVL MMC: command timed out\n");
+			return TIMEOUT;
+		}
+	}
+
+	/* Handling response */
+	for (resp_indx = 0 ; resp_indx < 8; resp_indx++)
+		response[resp_indx] = SDIO_REG_READ16(SDIO_RSP(resp_indx));
+
+	/* Copy the response to the response buffer */
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		cmd->response[0] = ((response[2] & 0x3f) << (8 - 8)) |
+				((response[1] & 0xffff) << (14 - 8)) |
+				((response[0] & 0x3ff) << (30 - 8));
+		if (cmd->resp_type & MMC_RSP_136) {
+			cmd->response[3] = ((response[7] & 0x3fff) << 8)	|
+					((response[6] & 0x3ff) << 22);
+			cmd->response[2] = ((response[6] & 0xfc00) >> 10)	|
+					((response[5] & 0xffff) << 6)	|
+					((response[4] & 0x3ff) << 22);
+			cmd->response[1] = ((response[4] & 0xfc00) >> 10)	|
+					((response[3] & 0xffff) << 6)	|
+					((response[2] & 0x3ff) << 22);
+			cmd->response[0] = ((response[2] & 0xfc00) >> 10)	|
+					((response[1] & 0xffff) << 6)	|
+					((response[0] & 0x3ff) << 22);
+		}
+	}
+
+#ifdef DEBUG
+	printf("resp index[0x%x] ", response[0] >> 10);
+	printf("[0x%x] ", cmd->response[0]);
+	printf("[0x%x] ", cmd->response[1]);
+	printf("[0x%x] ", cmd->response[2]);
+	printf("[0x%x] ", cmd->response[3]);
+	printf("\n");
+#endif
+
+	return 0;
+}
+
+static void mrvl_mmc_set_clk(unsigned long clk)
+{
+	unsigned int m;
+
+	m = MRVL_MMC_BASE_FAST_CLOCK/(2*clk) - 1;
+#ifdef DEBUG
+	printf("mrvl_mmc_set_clk: dividor = 0x%x clock=%d\n", m, clk);
+#endif
+	SDIO_REG_WRITE32(SDIO_CLK_DIV, m & 0x7ff);
+	udelay(10*1000);
+}
+
+static void mrvl_mmc_set_bus(unsigned int bus)
+{
+	ushort reg;
+
+#ifdef DEBUG
+	printf("mrvl_mmc_set_bus: bus = 0x%d\n", bus);
+#endif
+	reg = SDIO_REG_READ16(SDIO_HOST_CTRL);
+	reg &= ~(1 << 9);
+	switch (bus) {
+		case 4:
+			reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+			break;
+		case 1:
+		default:
+			reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
+	}
+	SDIO_REG_WRITE16(SDIO_HOST_CTRL, reg);
+	udelay(10*1000);
+}
+static void mrvl_mmc_set_ios(struct mmc *mmc)
+{
+#ifdef DEBUG
+	printf("bus[%d] clock[%d]\n", mmc->bus_width, mmc->clock);
+#endif
+	mrvl_mmc_set_bus(mmc->bus_width);
+	mrvl_mmc_set_clk(mmc->clock);
+}
+
+static int mrvl_mmc_init(struct mmc *mmc)
+{
+#ifdef DEBUG
+	printf("mrvl_mmc_init\n");
+#endif
+
+	/* Setting host parameters */
+	SDIO_REG_WRITE16(SDIO_HOST_CTRL,
+					SDIO_HOST_CTRL_TMOUT(0xf) |
+					SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
+					SDIO_HOST_CTRL_BIG_ENDIAN |
+					SDIO_HOST_CTRL_PUSH_PULL_EN |
+					SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY );
+	SDIO_REG_WRITE16(SDIO_CLK_CTRL, 0);
+
+	/* enable status */
+	SDIO_REG_WRITE16(SDIO_NOR_STATUS_EN, 0xffff);
+	SDIO_REG_WRITE16(SDIO_ERR_STATUS_EN, 0xffff);
+
+	/* disable interrupts */
+	SDIO_REG_WRITE16(SDIO_NOR_INTR_EN, 0);
+	SDIO_REG_WRITE16(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	SDIO_REG_WRITE16(SDIO_SW_RESET,0x100);
+	udelay(10000);
+	return 0;
+}
+
+int mrvl_mmc_initialize(bd_t *bis)
+{
+	struct mmc *mmc = NULL;
+
+	mmc = malloc(sizeof(struct mmc));
+	if (!mmc)
+		return -1;
+
+	sprintf(mmc->name, "MRVL_MMC");
+	mmc->send_cmd = mrvl_mmc_send_cmd;
+	mmc->set_ios = mrvl_mmc_set_ios;
+	mmc->init = mrvl_mmc_init;
+	
+	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->f_max = MRVL_MMC_CLOCKRATE_MAX;
+	mmc->f_min = MRVL_MMC_CLOCKRATE_MIN;
+	mmc->block_dev.part_type = PART_TYPE_DOS;
+
+	mmc_register(mmc);
+
+	return 0;
+}
diff --git a/include/mrvl_mmc.h b/include/mrvl_mmc.h
new file mode 100644
index 0000000..db3a15a
--- /dev/null
+++ b/include/mrvl_mmc.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lior Amsalem <alior@marvell.com>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MRVL_MMC_H__
+#define __MRVL_MMC_H__
+
+/* General definitions */
+#define P(x) (CONFIG_SYS_MMC_BASE + (x))
+#define SDIO_REG_WRITE32(addr,val) (*(volatile unsigned long*)(P(addr)) = val)
+#define SDIO_REG_WRITE16(addr,val) (*(volatile unsigned short*)(P(addr)) = val)
+#define SDIO_REG_READ16(addr) (*(volatile unsigned short*)(P(addr)))
+#define SDIO_REG_READ32(addr) (*(volatile unsigned long*)(P(addr)))
+
+//#define MVSDMMC_DMA_SIZE			65536
+//#define MVSDMMC_CMD_TIMEOUT			2 /* 100 usec*/
+
+/* The base MMC clock rate */
+#define MRVL_MMC_CLOCKRATE_MIN		250000
+#define MRVL_MMC_CLOCKRATE_MAX		50000000
+#define MRVL_MMC_BASE_FAST_CLOCK		200000000//100000000
+
+/* SDIO register */
+#define SDIO_SYS_ADDR_LOW			0x000
+#define SDIO_SYS_ADDR_HI			0x004
+#define SDIO_BLK_SIZE				0x008
+#define SDIO_BLK_COUNT				0x00c
+#define SDIO_ARG_LOW				0x010
+#define SDIO_ARG_HI					0x014
+#define SDIO_XFER_MODE				0x018
+#define SDIO_CMD					0x01c
+#define SDIO_RSP(i)					(0x020 + ((i)<<2))
+#define SDIO_RSP0					0x020
+#define SDIO_RSP1					0x024
+#define SDIO_RSP2					0x028
+#define SDIO_RSP3					0x02c
+#define SDIO_RSP4					0x030
+#define SDIO_RSP5					0x034
+#define SDIO_RSP6					0x038
+#define SDIO_RSP7					0x03c
+#define SDIO_BUF_DATA_PORT			0x040
+#define SDIO_RSVED					0x044
+#define SDIO_PRESENT_STATE0			0x048
+#define SDIO_PRESENT_STATE1			0x04c
+#define SDIO_HOST_CTRL				0x050
+#define SDIO_BLK_GAP_CTRL			0x054
+#define SDIO_CLK_CTRL				0x058
+#define SDIO_SW_RESET				0x05c
+#define SDIO_NOR_INTR_STATUS		0x060
+#define SDIO_ERR_INTR_STATUS		0x064
+#define SDIO_NOR_STATUS_EN			0x068
+#define SDIO_ERR_STATUS_EN			0x06c
+#define SDIO_NOR_INTR_EN			0x070
+#define SDIO_ERR_INTR_EN			0x074
+#define SDIO_AUTOCMD12_ERR_STATUS	0x078
+#define SDIO_CURR_BYTE_LEFT			0x07c
+#define SDIO_CURR_BLK_LEFT			0x080
+#define SDIO_AUTOCMD12_ARG_LOW		0x084
+#define SDIO_AUTOCMD12_ARG_HI		0x088
+#define SDIO_AUTOCMD12_INDEX		0x08c
+#define SDIO_AUTO_RSP(i)			(0x090 + ((i)<<2))
+#define SDIO_AUTO_RSP0				0x090
+#define SDIO_AUTO_RSP1				0x094
+#define SDIO_AUTO_RSP2				0x098
+#define SDIO_CLK_DIV				0x128
+
+#define WINDOW_CTRL(i)				(0x108 + ((i) << 3))
+#define WINDOW_BASE(i)				(0x10c + ((i) << 3))
+
+/* SDIO_PRESENT_STATE */
+#define CARD_BUSY				(1 << 1)
+#define CMD_INHIBIT				(1 << 0)
+#define CMD_TXACTIVE			(1 << 8)
+#define CMD_RXACTIVE			(1 << 9)
+#define CMD_AUTOCMD12ACTIVE		(1 << 14)
+#define CMD_BUS_BUSY			(CMD_AUTOCMD12ACTIVE |	\
+								CMD_RXACTIVE |	\
+								CMD_TXACTIVE |	\
+								CMD_INHIBIT |	\
+								CARD_BUSY)
+
+/* SDIO_CMD */
+#define SDIO_CMD_RSP_NONE				(0 << 0)
+#define SDIO_CMD_RSP_136				(1 << 0)
+#define SDIO_CMD_RSP_48					(2 << 0)
+#define SDIO_CMD_RSP_48BUSY				(3 << 0)
+#define SDIO_CMD_CHECK_DATACRC16		(1 << 2)
+#define SDIO_CMD_CHECK_CMDCRC			(1 << 3)
+#define SDIO_CMD_INDX_CHECK				(1 << 4)
+#define SDIO_CMD_DATA_PRESENT			(1 << 5)
+#define SDIO_UNEXPECTED_RESP			(1 << 7)
+
+/* SDIO_XFER_MODE */
+#define SDIO_XFER_MODE_STOP_CLK			(1 << 5)
+#define SDIO_XFER_MODE_HW_WR_DATA_EN	(1 << 1)
+#define SDIO_XFER_MODE_AUTO_CMD12		(1 << 2)
+#define SDIO_XFER_MODE_INT_CHK_EN		(1 << 3)
+#define SDIO_XFER_MODE_TO_HOST			(1 << 4)
+#define SDIO_XFER_MODE_DMA				(0 << 6)
+
+/* SDIO_HOST_CTRL */
+#define SDIO_HOST_CTRL_PUSH_PULL_EN				(1 << 0)
+#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY 		(0 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY 		(1 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO 	(2 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_MMC 			(3 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_MASK			(3 << 1)
+#define SDIO_HOST_CTRL_BIG_ENDIAN				(1 << 3)
+#define SDIO_HOST_CTRL_LSB_FIRST				(1 << 4)
+#define SDIO_HOST_CTRL_ID_MODE_LOW_FREQ			(1 << 5)
+#define SDIO_HOST_CTRL_HALF_SPEED				(1 << 6)
+#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT			(0 << 9)
+#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS		(1 << 9)
+#define SDIO_HOST_CTRL_HI_SPEED_EN				(1 << 10)
+#define SDIO_HOST_CTRL_TMOUT_MASK 				(0xf << 11)
+#define SDIO_HOST_CTRL_TMOUT_MAX 				(0xf << 11)
+#define SDIO_HOST_CTRL_TMOUT(x) 				((x) << 11)
+#define SDIO_HOST_CTRL_TMOUT_EN 				(1 << 15)
+#define SDIO_HOST_CTRL_DFAULT_OPEN_DRAIN		(SDIO_HOST_CTRL_TMOUT(x)(0xf))
+#define SDIO_HOST_CTRL_DFAULT_PUSH_PULL			(SDIO_HOST_CTRL_TMOUT(x)(0xf) | SDIO_HOST_CTRL_PUSH_PULL_EN)
+
+/* NOR status bits */
+#define SDIO_NOR_ERROR				(1 << 15)
+#define SDIO_NOR_UNEXP_RSP			(1 << 14)
+#define SDIO_NOR_AUTOCMD12_DONE		(1 << 13)
+#define SDIO_NOR_SUSPEND_ON			(1 << 12)
+#define SDIO_NOR_LMB_FF_8W_AVAIL	(1 << 11)
+#define SDIO_NOR_LMB_FF_8W_FILLED	(1 << 10)
+#define SDIO_NOR_READ_WAIT_ON		(1 << 9)
+#define SDIO_NOR_CARD_INT			(1 << 8)
+#define SDIO_NOR_READ_READY			(1 << 5)
+#define SDIO_NOR_WRITE_READY		(1 << 4)
+#define SDIO_NOR_DMA_INI			(1 << 3)
+#define SDIO_NOR_BLK_GAP_EVT		(1 << 2)
+#define SDIO_NOR_XFER_DONE			(1 << 1)
+#define SDIO_NOR_CMD_DONE			(1 << 0)
+
+/* ERR status bits */
+#define SDIO_ERR_CRC_STATUS			(1 << 14)
+#define SDIO_ERR_CRC_STARTBIT		(1 << 13)
+#define SDIO_ERR_CRC_ENDBIT			(1 << 12)
+#define SDIO_ERR_RESP_TBIT			(1 << 11)
+#define SDIO_ERR_SIZE				(1 << 10)
+#define SDIO_ERR_CMD_STARTBIT		(1 << 9)
+#define SDIO_ERR_AUTOCMD12			(1 << 8)
+#define SDIO_ERR_DATA_ENDBIT		(1 << 6)
+#define SDIO_ERR_DATA_CRC			(1 << 5)
+#define SDIO_ERR_DATA_TIMEOUT		(1 << 4)
+#define SDIO_ERR_CMD_INDEX			(1 << 3)
+#define SDIO_ERR_CMD_ENDBIT			(1 << 2)
+#define SDIO_ERR_CMD_CRC			(1 << 1)
+#define SDIO_ERR_CMD_TIMEOUT		(1 << 0)
+#define SDIO_POLL_MASK 				0xffff /* enable all for polling */
+
+/* MMC commands */
+#define MMC_BLOCK_SIZE				512
+#define MMC_CMD_RESET				0
+#define MMC_CMD_SEND_OP_COND		1
+#define MMC_CMD_ALL_SEND_CID		2
+#define MMC_CMD_SET_RCA				3
+#define MMC_CMD_SELECT_CARD			7
+#define MMC_CMD_SEND_CSD			9
+#define MMC_CMD_SEND_CID			10
+#define MMC_CMD_SEND_STATUS			13
+#define MMC_CMD_SET_BLOCKLEN		16
+#define MMC_CMD_READ_BLOCK			17
+#define MMC_CMD_RD_BLK_MULTI		18
+#define MMC_CMD_WRITE_BLOCK			24
+#define MMC_MAX_BLOCK_SIZE			512
+
+#endif /* __MRVL_MMC_H__ */
+
+int mrvl_mmc_initialize(bd_t *bis);
