From patchwork Sat Sep 22 02:05:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C60932C0084 for ; Sat, 22 Sep 2012 12:14:42 +1000 (EST) Received: from localhost ([::1]:42229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF6T-0006g3-F0 for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 22:05:57 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5x-0005Qf-Jq for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFF5v-0000oJ-QG for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:25 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:56041) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5v-0000d6-L2 for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:23 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so8850154pbb.4 for ; Fri, 21 Sep 2012 19:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=GXAUgQsR+bXds2RqUKHA6+IkhZJR/RrGbJPlSGzO9FI=; b=C2d7RCfGj17TyvPZQVOXdvBuN0vqZyRKNV4tLdbXYRuSC1vmcv5nypiozeo2Qo84GL W3k2Pda76NzZ/oIb5z8nrbjRzh/GcB7t7y8K0MJ4p3ffbjlVubAFa+VggAKfV1Iq2Ev5 R44YqkJY+qgdYwaB1AFAbFKUKTLtW2+/vBhy7p5M8txhWC6qkHrYMeb9m3WXQtKMYjHd Cq10niK0LKGRUGtJ9IpcnMNSNZ/3XoJqaHVE1mu39IjHw8wfIV5cWgpcNOgeLeMMBVxu Z5oAaEUQ6bfDV2K0nAKDGt9TC/GB8jQpXm0XSlxqO999N+m6YAn0Ccd4q0DmaQ+eL/+6 ghRA== Received: by 10.66.87.138 with SMTP id ay10mr17001323pab.38.1348279523334; Fri, 21 Sep 2012 19:05:23 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id s4sm4956298paw.35.2012.09.21.19.05.22 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Sep 2012 19:05:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 19:05:03 -0700 Message-Id: <1348279507-3617-11-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348279507-3617-1-git-send-email-rth@twiddle.net> References: <1348279507-3617-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 10/14] tcg-sparc: Mask shift immediates to avoid illegal insns. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index e625aa3..be5c170 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, goto gen_arith; case INDEX_op_shl_i32: c = SHIFT_SLL; - goto gen_arith; + do_shift32: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c); + break; case INDEX_op_shr_i32: c = SHIFT_SRL; - goto gen_arith; + goto do_shift32; case INDEX_op_sar_i32: c = SHIFT_SRA; - goto gen_arith; + goto do_shift32; case INDEX_op_mul_i32: c = ARITH_UMUL; goto gen_arith; @@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_shl_i64: c = SHIFT_SLLX; - goto gen_arith; + do_shift64: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c); + break; case INDEX_op_shr_i64: c = SHIFT_SRLX; - goto gen_arith; + goto do_shift64; case INDEX_op_sar_i64: c = SHIFT_SRAX; - goto gen_arith; + goto do_shift64; case INDEX_op_mul_i64: c = ARITH_MULX; goto gen_arith;