From patchwork Fri Sep 21 20:10:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: malc X-Patchwork-Id: 185909 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F03F52C0088 for ; Sat, 22 Sep 2012 06:10:43 +1000 (EST) Received: from localhost ([::1]:60717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF9Yf-0002mk-So for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 16:10:41 -0400 Received: from eggs.gnu.org ([208.118.235.92]:34399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF9YY-0002mH-Eo for qemu-devel@nongnu.org; Fri, 21 Sep 2012 16:10:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TF9YX-0004lz-6O for qemu-devel@nongnu.org; Fri, 21 Sep 2012 16:10:34 -0400 Received: from fe01x03-cgp.akado.ru ([77.232.31.164]:56815 helo=akado.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF9YW-0004jQ-OC for qemu-devel@nongnu.org; Fri, 21 Sep 2012 16:10:33 -0400 Received: from [10.0.66.9] ([10.0.66.9] verified) by fe01-cgp.akado.ru (CommuniGate Pro SMTP 5.2.13) with ESMTPS id 356586330; Sat, 22 Sep 2012 00:10:31 +0400 Date: Sat, 22 Sep 2012 00:10:21 +0400 (MSK) From: malc X-X-Sender: malc@linmac To: Richard Henderson In-Reply-To: <1348247620-12734-1-git-send-email-rth@twiddle.net> Message-ID: References: <1348247620-12734-1-git-send-email-rth@twiddle.net> User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 77.232.31.164 Cc: qemu-devel@nongnu.org, Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH v2 0/7] tcg: movcond (ppc32 version) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 26c4b33..0fb6fc7 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -390,6 +390,7 @@ static int tcg_target_const_match(tcg_target_long val, #define ORC XO31(412) #define EQV XO31(284) #define NAND XO31(476) +#define ISEL XO31( 15) #define LBZX XO31( 87) #define LHZX XO31(279) @@ -1269,6 +1270,75 @@ static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args, ); } +static void tcg_out_movcond (TCGContext *s, TCGCond cond, + TCGArg dest, + TCGArg c1, TCGArg c2, + TCGArg v1, TCGArg v2, + int const_c2) +{ + tcg_out_cmp (s, cond, c1, c2, const_c2, 7); + + if (1) { + /* At least here on 7747A bit twiddling hacks are outperformed + by jumpy code (the testing was not scientific) */ + void *label_ptr; + + if (dest == v2) { + label_ptr = s->code_ptr; + tcg_out32 (s, tcg_to_bc[tcg_invert_cond (cond)]); + tcg_out_mov (s, TCG_TYPE_I32, dest, v1); + reloc_pc14 (label_ptr, (tcg_target_long) s->code_ptr); + } + else { + tcg_out_mov (s, TCG_TYPE_I32, dest, v1); + label_ptr = s->code_ptr; + tcg_out32 (s, tcg_to_bc[cond]); + tcg_out_mov (s, TCG_TYPE_I32, dest, v2); + reloc_pc14 (label_ptr, (tcg_target_long) s->code_ptr); + } + } + else { + /* isel version, if (1) above should be replaced once a way to + figure out availability of isel on the underlying hardware + is found */ + int tab, bc; + + switch (cond) { + case TCG_COND_EQ: + tab = TAB (dest, v1, v2); + bc = CR_EQ; + break; + case TCG_COND_NE: + tab = TAB (dest, v2, v1); + bc = CR_EQ; + break; + case TCG_COND_LTU: + case TCG_COND_LT: + tab = TAB (dest, v1, v2); + bc = CR_LT; + break; + case TCG_COND_GEU: + case TCG_COND_GE: + tab = TAB (dest, v2, v1); + bc = CR_LT; + break; + case TCG_COND_LEU: + case TCG_COND_LE: + tab = TAB (dest, v2, v1); + bc = CR_GT; + break; + case TCG_COND_GTU: + case TCG_COND_GT: + tab = TAB (dest, v1, v2); + bc = CR_GT; + break; + default: + tcg_abort (); + } + tcg_out32 (s, ISEL | tab | ((bc + 28) << 6)); + } +} + static void tcg_out_brcond (TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, int label_index) @@ -1826,6 +1896,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, ); break; + case INDEX_op_movcond_i32: + tcg_out_movcond (s, args[5], args[0], + args[1], args[2], + args[3], args[4], + const_args[2]); + break; + default: tcg_dump_ops (s); tcg_abort (); @@ -1922,6 +1999,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_ext16u_i32, { "r", "r" } }, { INDEX_op_deposit_i32, { "r", "0", "r" } }, + { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "r" } }, { -1 }, }; diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 177eea1..3259d89 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -92,7 +92,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_AREG0 TCG_REG_R27