From patchwork Fri Sep 21 17:13:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 185861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 015322C0079 for ; Sat, 22 Sep 2012 03:54:23 +1000 (EST) Received: from localhost ([::1]:43140 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6or-0007hF-VC for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 13:15:13 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6o7-00062h-CR for qemu-devel@nongnu.org; Fri, 21 Sep 2012 13:14:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TF6o6-0003Pa-0u for qemu-devel@nongnu.org; Fri, 21 Sep 2012 13:14:27 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:43448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6o5-0003NU-S2 for qemu-devel@nongnu.org; Fri, 21 Sep 2012 13:14:25 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so8127923pbb.4 for ; Fri, 21 Sep 2012 10:14:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Muis1VIPU8xjjMsY6m6PTMgeZ8wTPsOK8Gj0z/I0xmo=; b=AIHuJz2xdKGBegWMko+FmHprDJKi6tOmLdfwKXgW7CcIrKttANPkdx6zTFdp0UYbPf PCR6hY19ODi9itKvad01SbkmMqr+rC6WvwX6OIya74B8QqEx+kv3ZnWlxTUNFfLib4vp /uJX+70kJiohKg3Z503cB6/ztfWa8C6qh68wBpYqv9Xi7zeX9k2QDQ40ozgJ+8CtA5/v Ciutp6ZU29kBq3PreQPz4bLoiidb/HK8/ckErhldvsXEOdyRvpnNQsZnBEO2gNjYDTlj Da2Qiuj5x3Xq2R3dlN8yHwVBCNsrGMqW0T8zFFPWEC1/dqTDn7qjOy/gT9ixltMWQ0k7 fVgg== Received: by 10.68.232.131 with SMTP id to3mr17530620pbc.58.1348247665596; Fri, 21 Sep 2012 10:14:25 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id gf8sm5389723pbc.52.2012.09.21.10.14.24 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Sep 2012 10:14:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 10:13:40 -0700 Message-Id: <1348247620-12734-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348247620-12734-1-git-send-email-rth@twiddle.net> References: <1348247620-12734-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 7/7] tcg: Streamline movcond_i64 using movcond_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When movcond_i32 is available we can further reduce the generated op count from 12 to 6, and the generated code size on i686 from 88 to 74 bytes. Signed-off-by: Richard Henderson Tested-by: Aurelien Jarno Reviewed-by: Aurelien Jarno --- tcg/tcg-op.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 3e375ea..0145a09 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2147,16 +2147,24 @@ static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, TCGV_LOW(c1), TCGV_HIGH(c1), TCGV_LOW(c2), TCGV_HIGH(c2), cond); - tcg_gen_neg_i32(t0, t0); - tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); - tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + if (TCG_TARGET_HAS_movcond_i32) { + tcg_gen_movi_i32(t1, 0); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, + TCGV_LOW(v1), TCGV_LOW(v2)); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, + TCGV_HIGH(v1), TCGV_HIGH(v2)); + } else { + tcg_gen_neg_i32(t0, t0); - tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); - tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); + tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); + tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); } else {