From patchwork Fri Sep 21 16:43:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 185855 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 880C82C0085 for ; Sat, 22 Sep 2012 03:31:30 +1000 (EST) Received: from localhost ([::1]:44258 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6L8-0008L6-DG for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 12:44:30 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6KV-0006jc-9e for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TF6KO-000852-6f for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:51 -0400 Received: from hall.aurel32.net ([88.191.126.93]:43340) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TF6KN-00084W-Uk for qemu-devel@nongnu.org; Fri, 21 Sep 2012 12:43:44 -0400 Received: from [37.160.47.140] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TF6KM-0003it-LL; Fri, 21 Sep 2012 18:43:42 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TF6KC-0003r2-Be; Fri, 21 Sep 2012 18:43:32 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 18:43:27 +0200 Message-Id: <1348245809-13482-9-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1348245809-13482-1-git-send-email-aurelien@aurel32.net> References: <1348245809-13482-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 08/10] tcg/mips: implement rotl/rotr ops on MIPS32R2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org rotr operations can be optimized on MIPS32 Release 2 using the ROTR and ROTRV instructions. Also implemented rotl operations by subtracting the shift from 32. Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 20 ++++++++++++++++++++ tcg/mips/tcg-target.h | 3 ++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 8b2f9fc..592e42a 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -300,9 +300,11 @@ enum { OPC_SPECIAL = 0x00 << 26, OPC_SLL = OPC_SPECIAL | 0x00, OPC_SRL = OPC_SPECIAL | 0x02, + OPC_ROTR = OPC_SPECIAL | (0x01 << 21) | 0x02, OPC_SRA = OPC_SPECIAL | 0x03, OPC_SLLV = OPC_SPECIAL | 0x04, OPC_SRLV = OPC_SPECIAL | 0x06, + OPC_ROTRV = OPC_SPECIAL | (0x01 << 6) | 0x06, OPC_SRAV = OPC_SPECIAL | 0x07, OPC_JR = OPC_SPECIAL | 0x08, OPC_JALR = OPC_SPECIAL | 0x09, @@ -1420,6 +1422,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_reg(s, OPC_SRLV, args[0], args[2], args[1]); } break; + case INDEX_op_rotl_i32: + if (const_args[2]) { + tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], 0x20 - args[2]); + } else { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_AT, 32); + tcg_out_opc_reg(s, OPC_SUBU, TCG_REG_AT, TCG_REG_AT, args[2]); + tcg_out_opc_reg(s, OPC_ROTRV, args[0], TCG_REG_AT, args[1]); + } + break; + case INDEX_op_rotr_i32: + if (const_args[2]) { + tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], args[2]); + } else { + tcg_out_opc_reg(s, OPC_ROTRV, args[0], args[2], args[1]); + } + break; /* The bswap routines do not work on non-R2 CPU. In that case we let TCG generating the corresponding code. */ @@ -1523,6 +1541,8 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, + { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, + { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, { INDEX_op_bswap16_i32, { "r", "r" } }, { INDEX_op_bswap32_i32, { "r", "r" } }, diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c5c13f7..470314c 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -80,7 +80,6 @@ typedef enum { #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_andc_i32 0 @@ -94,9 +93,11 @@ typedef enum { #ifdef _MIPS_ARCH_MIPS32R2 #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 +#define TCG_TARGET_HAS_rot_i32 1 #else #define TCG_TARGET_HAS_bswap16_i32 0 #define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_rot_i32 0 #endif /* optional instructions automatically implemented */