Patchwork memsets to 0 over 256 bytes are broken on PowerPC 405

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Submitter Jason Gunthorpe
Date Sept. 21, 2012, 5:01 p.m.
Message ID <20120921170100.GB30101@obsidianresearch.com>
Download mbox | patch
Permalink /patch/185841/
State New
Headers show

Comments

Jason Gunthorpe - Sept. 21, 2012, 5:01 p.m.
The use_dcbz path in the hand coded assembly is assuming a 128 byte
clear size for dcbz, but dcbz uses the cache line size and 405 cores
only have a 32 byte cache line. So any clears to 0 that use the dcbz
path fail to work.

Some high end PPC's have a 128 byte cache line, but all 405's are 32
byte, see arch/powerpc/kernel/cputable.c, dcache_bsize
assignments. This value flows from the kernel to glibc's
__cache_line_size value which drives the dcbz step in the generic
memset.

Fix 405 memset.s to align and step the dcbz path to 32 byte cache
lines.

See http://sourceware.org/bugzilla/show_bug.cgi?id=14595
---
 .../ports-2_13/100-powerpc-405-broken-memset.patch |   45 ++++++++++++++++++++
 1 files changed, 45 insertions(+), 0 deletions(-)
 create mode 100644 patches/eglibc/ports-2_13/100-powerpc-405-broken-memset.patch

This bug is present in all glibc's and eglibcs since at least 2.3.5
and results in PPC405 being completely broken. I've submitted it to
glib-ports bugzilla and will forward to that mailing list as well..

Patch

diff --git a/patches/eglibc/ports-2_13/100-powerpc-405-broken-memset.patch b/patches/eglibc/ports-2_13/100-powerpc-405-broken-memset.patch
new file mode 100644
index 0000000..d2c0a88
--- /dev/null
+++ b/patches/eglibc/ports-2_13/100-powerpc-405-broken-memset.patch
@@ -0,0 +1,45 @@ 
+memsets to 0 over 256 bytes are broken on PowerPC 405
+
+The use_dcbz path in the hand coded assembly is assuming a 128 byte clear size
+for dcbz, but dcbz uses the cache line size and 405 cores only have a 32 byte
+cache line. So any clears to 0 that use the dcbz path fail to work.
+
+Some high end PPC's have a 128 byte cache line, but all 405's are 32 byte,
+see arch/powerpc/kernel/cputable.c, dcache_bsize assignments. This value
+flows from the kernel to glibc's __cache_line_size value which drives
+the dcbz step in the generic memset.
+
+Fix 405 memset.s to align and step the dcbz path to 32 byte cache lines.
+
+See
+http://sourceware.org/bugzilla/show_bug.cgi?id=14595
+
+--- eglibc-2_13.orig/ports/sysdeps/powerpc/powerpc32/405/memset.S	2012-09-18 23:06:38.743817536 -0600
++++ eglibc-2_13/ports/sysdeps/powerpc/powerpc32/405/memset.S	2012-09-18 23:09:48.677194920 -0600
+@@ -105,7 +105,7 @@
+        add     r3,r3,r7
+ 
+ L(skip_string_loop):
+-       clrlwi  r8,r6,25
++       clrlwi  r8,r6,27
+        srwi.   r8,r8,4
+        beq     L(dcbz_pre_loop)
+        mtctr   r8
+@@ -120,14 +120,14 @@
+        bdnz    L(word_loop)
+ 
+ L(dcbz_pre_loop):
+-       srwi    r6,r5,7
++       srwi    r6,r5,5
+        mtctr   r6
+        addi    r7,0,0
+ 
+ L(dcbz_loop):
+        dcbz    r3,r7
+-       addi    r3,r3,0x80
+-       subi    r5,r5,0x80
++       addi    r3,r3,32
++       subi    r5,r5,32
+        bdnz    L(dcbz_loop)
+        srwi.   r6,r5,4
+        beq     L(postword2_count_loop)