| Message ID | 1348080408-30686-1-git-send-email-eric.nelson@boundarydevices.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
On 09/19/2012 11:46 AM, Eric Nelson wrote: > Adds support for the Hannstar 1024 x 768 LVDS panel (Freescale part > number MCIMX-LVDS1) to SABRE-Lite board. > > Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com> > --- > board/freescale/mx6qsabrelite/mx6qsabrelite.c | 102 +++++++++++++++++++++++++ > include/configs/mx6qsabrelite.h | 15 ++++- > 2 files changed, 116 insertions(+), 1 deletions(-) > > diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > index 4b4e89b..c42a6ab 100644 > --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c > +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > @@ -36,6 +36,9 @@ > #include<micrel.h> > #include<miiphy.h> > #include<netdev.h> > +#include<linux/fb.h> > +#include<ipu_pixfmt.h> > +#include<asm/arch/crm_regs.h> > DECLARE_GLOBAL_DATA_PTR; > > #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ > @@ -195,6 +198,10 @@ static iomux_v3_cfg_t button_pads[] = { > MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), > }; > > +iomux_v3_cfg_t lcd_gpio[] = { > + MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > static void setup_iomux_enet(void) > { > gpio_direction_output(IMX_GPIO_NR(3, 23), 0); > @@ -372,14 +379,106 @@ int setup_sata(void) > } > #endif > > +static struct fb_videomode lvds_xga = { > + .name = "Hannstar-XGA", > + .refresh = 60, > + .xres = 1024, > + .yres = 768, > + .pixclock = 15385, > + .left_margin = 220, > + .right_margin = 40, > + .upper_margin = 21, > + .lower_margin = 7, > + .hsync_len = 60, > + .vsync_len = 10, > + .sync = FB_SYNC_EXT, > + .vmode = FB_VMODE_NONINTERLACED > +}; > + > +void lcd_iomux(void) > +{ > + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; > + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; > + > + int reg; > + > + /* Turn on GPIO backlight */ > + imx_iomux_v3_setup_multiple_pads(lcd_gpio, ARRAY_SIZE(lcd_gpio)); > + gpio_direction_output(18, 1); > + > + /* Turn on LDB0,IPU,IPU DI0 clocks */ > + reg = __raw_readl(&mxc_ccm->CCGR3); > + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK > + |MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK > + |MXC_CCM_CCGR3_LDB_DI0_MASK; > + writel(reg,&mxc_ccm->CCGR3); > + > + /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ > + writel(ANATOP_PFD_480_PFD1_FRAC_MASK,&anatop->pfd_480_clr); > + writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT,&anatop->pfd_480_set); > + > + /* set LDB0, LDB1 clk select to 011/011 */ > + reg = readl(&mxc_ccm->cs2cdr); > + reg&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK > + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); > + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) > + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); > + writel(reg,&mxc_ccm->cs2cdr); > + > + reg = readl(&mxc_ccm->cscmr2); > + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; > + writel(reg,&mxc_ccm->cscmr2); > + > + reg = readl(&mxc_ccm->chsccdr); > + reg&= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK > + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK > + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); > + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 > + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) > + |(CHSCCDR_PODF_DIVIDE_BY_3 > + <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) > + |(CHSCCDR_IPU_PRE_CLK_540M_PFD > + <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); > + writel(reg,&mxc_ccm->chsccdr); > + > + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES > + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH > + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW > + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG > + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT > + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG > + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT > + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED > + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; > + writel(0x201,&iomux->gpr[2]); err.. reg? If I spent that much time setting it up, I shoulda used it. Looking more closely, I think GPR3 is also going to need some setup.
On 09/19/2012 11:46 AM, Eric Nelson wrote: > Adds support for the Hannstar 1024 x 768 LVDS panel (Freescale part > number MCIMX-LVDS1) to SABRE-Lite board. > > Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com> > --- > board/freescale/mx6qsabrelite/mx6qsabrelite.c | 102 +++++++++++++++++++++++++ > include/configs/mx6qsabrelite.h | 15 ++++- > 2 files changed, 116 insertions(+), 1 deletions(-) > > diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > index 4b4e89b..c42a6ab 100644 > --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c > +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > @@ -36,6 +36,9 @@ > #include<micrel.h> > #include<miiphy.h> > #include<netdev.h> > +#include<linux/fb.h> > +#include<ipu_pixfmt.h> > +#include<asm/arch/crm_regs.h> > DECLARE_GLOBAL_DATA_PTR; > > <snip> > Please disregard. V4 forthcoming with fix for CCGR reference as mentioned here: http://lists.denx.de/pipermail/u-boot/2012-September/134550.html Regards, Eric
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 4b4e89b..c42a6ab 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -36,6 +36,9 @@ #include <micrel.h> #include <miiphy.h> #include <netdev.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/arch/crm_regs.h> DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ @@ -195,6 +198,10 @@ static iomux_v3_cfg_t button_pads[] = { MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), }; +iomux_v3_cfg_t lcd_gpio[] = { + MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_enet(void) { gpio_direction_output(IMX_GPIO_NR(3, 23), 0); @@ -372,14 +379,106 @@ int setup_sata(void) } #endif +static struct fb_videomode lvds_xga = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + +void lcd_iomux(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg; + + /* Turn on GPIO backlight */ + imx_iomux_v3_setup_multiple_pads(lcd_gpio, ARRAY_SIZE(lcd_gpio)); + gpio_direction_output(18, 1); + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK + |MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK + |MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ + writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); + writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + |(CHSCCDR_PODF_DIVIDE_BY_3 + <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + |(CHSCCDR_IPU_PRE_CLK_540M_PFD + <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(0x201, &iomux->gpr[2]); +} + +void lcd_enable(void) +{ + int ret = ipuv3_fb_init(&lvds_xga, 0, IPU_PIX_FMT_RGB666); + if (ret) + printf("LCD %s cannot be configured: %d\n", lvds_xga.name, ret); +} + int board_early_init_f(void) { setup_iomux_uart(); setup_buttons(); + lcd_iomux(); return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_init(void) { /* address of boot parameters */ @@ -396,6 +495,9 @@ int board_init(void) setup_sata(); #endif +#ifdef CONFIG_VIDEO + lcd_enable(); +#endif return 0; } diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 72d0154..d0c3e0a 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -39,7 +39,7 @@ #define CONFIG_REVISION_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R @@ -121,6 +121,19 @@ /* Miscellaneous commands */ #define CONFIG_CMD_BMODE +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1
Adds support for the Hannstar 1024 x 768 LVDS panel (Freescale part number MCIMX-LVDS1) to SABRE-Lite board. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 102 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 15 ++++- 2 files changed, 116 insertions(+), 1 deletions(-)