From patchwork Wed Sep 19 18:17:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Nelson X-Patchwork-Id: 185129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A6D232C0085 for ; Thu, 20 Sep 2012 04:17:59 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6911928098; Wed, 19 Sep 2012 20:17:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A5kb+eF2OnSw; Wed, 19 Sep 2012 20:17:58 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7BDB828099; Wed, 19 Sep 2012 20:17:55 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3EF9328099 for ; Wed, 19 Sep 2012 20:17:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2AritiFGg12k for ; Wed, 19 Sep 2012 20:17:50 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.integraonline.com (relay1.integra.net [204.130.255.180]) by theia.denx.de (Postfix) with SMTP id AC8DB28098 for ; Wed, 19 Sep 2012 20:17:47 +0200 (CEST) Received: (qmail 2688 invoked from network); 19 Sep 2012 18:17:45 -0000 Received: from unknown (HELO ericsony.example.org) (70.96.116.236) by relay1.integra.net with SMTP; 19 Sep 2012 18:17:45 -0000 From: Eric Nelson To: u-boot@lists.denx.de Date: Wed, 19 Sep 2012 11:17:42 -0700 Message-Id: <1348078662-13933-1-git-send-email-eric.nelson@boundarydevices.com> X-Mailer: git-send-email 1.7.9 Subject: [U-Boot] [PATCH] i.MX6: provide functional names for CCGRx bit fields X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Eric Nelson --- arch/arm/cpu/armv7/mx6/clock.c | 10 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 358 +++++++++++++++--------------- 2 files changed, 185 insertions(+), 183 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fddb373..ed2c913 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -43,9 +43,9 @@ void enable_usboh3_clk(unsigned char enable) reg = __raw_readl(&imx_ccm->CCGR6); if (enable) - reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET; + reg |= MXC_CCM_CCGR6_USBOH3_MASK; else - reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET); + reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); __raw_writel(reg, &imx_ccm->CCGR6); } @@ -59,7 +59,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) if (i2c_num > 2) return -EINVAL; - mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1); + + mask = MXC_CCM_CCGR_CG_MASK + << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1)); reg = __raw_readl(&imx_ccm->CCGR2); if (enable) reg |= mask; @@ -321,7 +323,7 @@ int enable_sata_clock(void) /* Enable sata clock */ reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ - reg |= MXC_CCM_CCGR5_CG2_MASK; + reg |= MXC_CCM_CCGR5_SATA_MASK; writel(reg, &imx_ccm->CCGR5); /* Enable PLLs */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 8388e38..f066461 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -395,185 +395,185 @@ struct mxc_ccm_reg { /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 3 -#define MXC_CCM_CCGR0_CG15_OFFSET 30 -#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) -#define MXC_CCM_CCGR0_CG14_OFFSET 28 -#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR0_CG13_OFFSET 26 -#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR0_CG12_OFFSET 24 -#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR0_CG11_OFFSET 22 -#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR0_CG10_OFFSET 20 -#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR0_CG9_OFFSET 18 -#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR0_CG8_OFFSET 16 -#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR0_CG7_OFFSET 14 -#define MXC_CCM_CCGR0_CG6_OFFSET 12 -#define MXC_CCM_CCGR0_CG5_OFFSET 10 -#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) -#define MXC_CCM_CCGR0_CG4_OFFSET 8 -#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) -#define MXC_CCM_CCGR0_CG3_OFFSET 6 -#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) -#define MXC_CCM_CCGR0_CG2_OFFSET 4 -#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR0_CG1_OFFSET 2 -#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) -#define MXC_CCM_CCGR0_CG0_OFFSET 0 -#define MXC_CCM_CCGR0_CG0_MASK 3 - -#define MXC_CCM_CCGR1_CG15_OFFSET 30 -#define MXC_CCM_CCGR1_CG14_OFFSET 28 -#define MXC_CCM_CCGR1_CG13_OFFSET 26 -#define MXC_CCM_CCGR1_CG12_OFFSET 24 -#define MXC_CCM_CCGR1_CG11_OFFSET 22 -#define MXC_CCM_CCGR1_CG10_OFFSET 20 -#define MXC_CCM_CCGR1_CG9_OFFSET 18 -#define MXC_CCM_CCGR1_CG8_OFFSET 16 -#define MXC_CCM_CCGR1_CG7_OFFSET 14 -#define MXC_CCM_CCGR1_CG6_OFFSET 12 -#define MXC_CCM_CCGR1_CG5_OFFSET 10 -#define MXC_CCM_CCGR1_CG4_OFFSET 8 -#define MXC_CCM_CCGR1_CG3_OFFSET 6 -#define MXC_CCM_CCGR1_CG2_OFFSET 4 -#define MXC_CCM_CCGR1_CG1_OFFSET 2 -#define MXC_CCM_CCGR1_CG0_OFFSET 0 - -#define MXC_CCM_CCGR2_CG15_OFFSET 30 -#define MXC_CCM_CCGR2_CG14_OFFSET 28 -#define MXC_CCM_CCGR2_CG13_OFFSET 26 -#define MXC_CCM_CCGR2_CG12_OFFSET 24 -#define MXC_CCM_CCGR2_CG11_OFFSET 22 -#define MXC_CCM_CCGR2_CG10_OFFSET 20 -#define MXC_CCM_CCGR2_CG9_OFFSET 18 -#define MXC_CCM_CCGR2_CG8_OFFSET 16 -#define MXC_CCM_CCGR2_CG7_OFFSET 14 -#define MXC_CCM_CCGR2_CG6_OFFSET 12 -#define MXC_CCM_CCGR2_CG5_OFFSET 10 -#define MXC_CCM_CCGR2_CG4_OFFSET 8 -#define MXC_CCM_CCGR2_CG3_OFFSET 6 -#define MXC_CCM_CCGR2_CG2_OFFSET 4 -#define MXC_CCM_CCGR2_CG1_OFFSET 2 -#define MXC_CCM_CCGR2_CG0_OFFSET 0 - -#define MXC_CCM_CCGR3_CG15_OFFSET 30 -#define MXC_CCM_CCGR3_CG14_OFFSET 28 -#define MXC_CCM_CCGR3_CG13_OFFSET 26 -#define MXC_CCM_CCGR3_CG12_OFFSET 24 -#define MXC_CCM_CCGR3_CG11_OFFSET 22 -#define MXC_CCM_CCGR3_CG10_OFFSET 20 -#define MXC_CCM_CCGR3_CG9_OFFSET 18 -#define MXC_CCM_CCGR3_CG8_OFFSET 16 -#define MXC_CCM_CCGR3_CG7_OFFSET 14 -#define MXC_CCM_CCGR3_CG6_OFFSET 12 -#define MXC_CCM_CCGR3_CG5_OFFSET 10 -#define MXC_CCM_CCGR3_CG4_OFFSET 8 -#define MXC_CCM_CCGR3_CG3_OFFSET 6 -#define MXC_CCM_CCGR3_CG2_OFFSET 4 -#define MXC_CCM_CCGR3_CG1_OFFSET 2 -#define MXC_CCM_CCGR3_CG0_OFFSET 0 - -#define MXC_CCM_CCGR4_CG15_OFFSET 30 -#define MXC_CCM_CCGR4_CG14_OFFSET 28 -#define MXC_CCM_CCGR4_CG13_OFFSET 26 -#define MXC_CCM_CCGR4_CG12_OFFSET 24 -#define MXC_CCM_CCGR4_CG11_OFFSET 22 -#define MXC_CCM_CCGR4_CG10_OFFSET 20 -#define MXC_CCM_CCGR4_CG9_OFFSET 18 -#define MXC_CCM_CCGR4_CG8_OFFSET 16 -#define MXC_CCM_CCGR4_CG7_OFFSET 14 -#define MXC_CCM_CCGR4_CG6_OFFSET 12 -#define MXC_CCM_CCGR4_CG5_OFFSET 10 -#define MXC_CCM_CCGR4_CG4_OFFSET 8 -#define MXC_CCM_CCGR4_CG3_OFFSET 6 -#define MXC_CCM_CCGR4_CG2_OFFSET 4 -#define MXC_CCM_CCGR4_CG1_OFFSET 2 -#define MXC_CCM_CCGR4_CG0_OFFSET 0 - -#define MXC_CCM_CCGR5_CG15_OFFSET 30 -#define MXC_CCM_CCGR5_CG14_OFFSET 28 -#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR5_CG13_OFFSET 26 -#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR5_CG12_OFFSET 24 -#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR5_CG11_OFFSET 22 -#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR5_CG10_OFFSET 20 -#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR5_CG9_OFFSET 18 -#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR5_CG8_OFFSET 16 -#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR5_CG7_OFFSET 14 -#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) -#define MXC_CCM_CCGR5_CG6_OFFSET 12 -#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) -#define MXC_CCM_CCGR5_CG5_OFFSET 10 -#define MXC_CCM_CCGR5_CG4_OFFSET 8 -#define MXC_CCM_CCGR5_CG3_OFFSET 6 -#define MXC_CCM_CCGR5_CG2_OFFSET 4 -#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR5_CG1_OFFSET 2 -#define MXC_CCM_CCGR5_CG0_OFFSET 0 - -#define MXC_CCM_CCGR6_CG15_OFFSET 30 -#define MXC_CCM_CCGR6_CG14_OFFSET 28 -#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR6_CG13_OFFSET 26 -#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR6_CG12_OFFSET 24 -#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR6_CG11_OFFSET 22 -#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR6_CG10_OFFSET 20 -#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR6_CG9_OFFSET 18 -#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR6_CG8_OFFSET 16 -#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR6_CG7_OFFSET 14 -#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) -#define MXC_CCM_CCGR6_CG6_OFFSET 12 -#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) -#define MXC_CCM_CCGR6_CG5_OFFSET 10 -#define MXC_CCM_CCGR6_CG4_OFFSET 8 -#define MXC_CCM_CCGR6_CG3_OFFSET 6 -#define MXC_CCM_CCGR6_CG2_OFFSET 4 -#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR6_CG1_OFFSET 2 -#define MXC_CCM_CCGR6_CG0_OFFSET 0 - -#define MXC_CCM_CCGR7_CG15_OFFSET 30 -#define MXC_CCM_CCGR7_CG14_OFFSET 28 -#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGR7_CG13_OFFSET 26 -#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGR7_CG12_OFFSET 24 -#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGR7_CG11_OFFSET 22 -#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGR7_CG10_OFFSET 20 -#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGR7_CG9_OFFSET 18 -#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGR7_CG8_OFFSET 16 -#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGR7_CG7_OFFSET 14 -#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) -#define MXC_CCM_CCGR7_CG6_OFFSET 12 -#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) -#define MXC_CCM_CCGR7_CG5_OFFSET 10 -#define MXC_CCM_CCGR7_CG4_OFFSET 8 -#define MXC_CCM_CCGR7_CG3_OFFSET 6 -#define MXC_CCM_CCGR7_CG2_OFFSET 4 -#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGR7_CG1_OFFSET 2 -#define MXC_CCM_CCGR7_CG0_OFFSET 0 +#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 +#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<