From patchwork Wed Sep 19 00:23:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 184896 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 738AA2C0086 for ; Wed, 19 Sep 2012 10:59:33 +1000 (EST) Received: from localhost ([::1]:40097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE86S-0002iu-Ct for incoming@patchwork.ozlabs.org; Tue, 18 Sep 2012 20:25:20 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE85b-0000aj-5A for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TE85Y-00055Y-Ly for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:27 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:61843) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE85Y-00052h-2J for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:24 -0400 Received: by mail-lpp01m010-f45.google.com with SMTP id z14so273861lag.4 for ; Tue, 18 Sep 2012 17:24:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=sZIHV9Fc850Gb24FZKPgEdP0D3cqjVuVRE55BtazAwg=; b=o9k3U5p2FavWUD+vLEGDnH4AMVbgpagZ7Gm04H47W1WPXnbe0WG9BepW3fmKfUqHiK 7wa4elDyz8jAnjBTenjRfW44zX1G0NfUx10Wk2l3S7OJdQIo8UuzZNq5jZfKmZMeNpjU VPxYWi6YAp5aywj6XNJ57MzeOC3mjsDd38bZNy8ODLpkzTpd75mWt9n0zn3tPFMkkJ0A tkE1zBGFrj8dpQtdrayJgoPuGJ5yrG8Khokh2fFEhq6lwwhHakeuLyxW6GAtGEb7GZb6 p7O+YVz2n2xhVX6FZKT3WQD09u1xnbK0sUEqs7sMpPKp9ECIp0pRm9UGSn26eJVXLB9a aNRg== Received: by 10.152.46.209 with SMTP id x17mr1174790lam.38.1348014263599; Tue, 18 Sep 2012 17:24:23 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id hh10sm236651lab.10.2012.09.18.17.24.22 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Sep 2012 17:24:22 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 19 Sep 2012 04:23:59 +0400 Message-Id: <1348014239-6233-11-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1348014239-6233-1-git-send-email-jcmvbkbc@gmail.com> References: <1348014239-6233-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.215.45 Cc: Blue Swirl , Peter Maydell , Max Filippov Subject: [Qemu-devel] [PATCH v3 10/10] target-xtensa: implement coprocessor context option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In case Coprocessor Context option is enabled CPENABLE SR bits control whether access to coprocessors is allowed or would rise one of CoprocessorXDisabled exceptions. See ISA, 4.4.5 for more details. FP is coprocessor 0. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 5 +++++ target-xtensa/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 0 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index b456283..7348277 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -468,6 +468,8 @@ static inline int cpu_mmu_index(CPUXtensaState *env) #define XTENSA_TBFLAG_LITBASE 0x8 #define XTENSA_TBFLAG_DEBUG 0x10 #define XTENSA_TBFLAG_ICOUNT 0x20 +#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 +#define XTENSA_TBFLAG_CPENABLE_SHIFT 6 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -491,6 +493,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, *flags |= XTENSA_TBFLAG_ICOUNT; } } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } } #include "cpu-all.h" diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 652f9bb..0a1d190 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -65,6 +65,8 @@ typedef struct DisasContext { bool debug; bool icount; TCGv_i32 next_icount; + + unsigned cpenable; } DisasContext; static TCGv_ptr cpu_env; @@ -331,6 +333,15 @@ static void gen_check_privilege(DisasContext *dc) } } +static void gen_check_cpenable(DisasContext *dc, unsigned cp) +{ + if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && + !(dc->cpenable & (1 << cp))) { + gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); + dc->is_jmp = DISAS_UPDATE; + } +} + static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) { tcg_gen_mov_i32(cpu_pc, dest); @@ -579,6 +590,13 @@ static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) } } +static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) +{ + tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); +} + static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) { tcg_gen_andi_i32(cpu_SR[sr], v, @@ -681,6 +699,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) [DBREAKA + 1] = gen_wsr_dbreaka, [DBREAKC] = gen_wsr_dbreakc, [DBREAKC + 1] = gen_wsr_dbreakc, + [CPENABLE] = gen_wsr_cpenable, [INTSET] = gen_wsr_intset, [INTCLEAR] = gen_wsr_intclear, [INTENABLE] = gen_wsr_intenable, @@ -1832,6 +1851,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 5: /*SSXUf*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); gen_window_check2(dc, RRR_S, RRR_T); + gen_check_cpenable(dc, 0); { TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); @@ -1891,26 +1911,31 @@ static void disas_xtensa_insn(DisasContext *dc) HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); switch (OP2) { case 0: /*ADD.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_add_s(cpu_FR[RRR_R], cpu_env, cpu_FR[RRR_S], cpu_FR[RRR_T]); break; case 1: /*SUB.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, cpu_FR[RRR_S], cpu_FR[RRR_T]); break; case 2: /*MUL.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, cpu_FR[RRR_S], cpu_FR[RRR_T]); break; case 4: /*MADD.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); break; case 5: /*MSUB.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); break; @@ -1921,6 +1946,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 11: /*CEIL.Sf*/ case 14: /*UTRUNC.Sf*/ gen_window_check1(dc, RRR_R); + gen_check_cpenable(dc, 0); { static const unsigned rounding_mode_const[] = { float_round_nearest_even, @@ -1949,6 +1975,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 12: /*FLOAT.Sf*/ case 13: /*UFLOAT.Sf*/ gen_window_check1(dc, RRR_S); + gen_check_cpenable(dc, 0); { TCGv_i32 scale = tcg_const_i32(-RRR_T); @@ -1966,24 +1993,29 @@ static void disas_xtensa_insn(DisasContext *dc) case 15: /*FP1OP*/ switch (RRR_T) { case 0: /*MOV.Sf*/ + gen_check_cpenable(dc, 0); tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); break; case 1: /*ABS.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); break; case 4: /*RFRf*/ gen_window_check1(dc, RRR_R); + gen_check_cpenable(dc, 0); tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); break; case 5: /*WFRf*/ gen_window_check1(dc, RRR_S); + gen_check_cpenable(dc, 0); tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); break; case 6: /*NEG.Sf*/ + gen_check_cpenable(dc, 0); gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); break; @@ -2006,6 +2038,7 @@ static void disas_xtensa_insn(DisasContext *dc) do { \ TCGv_i32 bit = tcg_const_i32(1 << br); \ \ + gen_check_cpenable(dc, 0); \ gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ tcg_temp_free(bit); \ } while (0) @@ -2046,6 +2079,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 10: /*MOVLTZ.Sf*/ case 11: /*MOVGEZ.Sf*/ gen_window_check1(dc, RRR_T); + gen_check_cpenable(dc, 0); { static const TCGCond cond[] = { TCG_COND_NE, @@ -2063,6 +2097,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 12: /*MOVF.Sf*/ case 13: /*MOVT.Sf*/ HAS_OPTION(XTENSA_OPTION_BOOLEAN); + gen_check_cpenable(dc, 0); { int label = gen_new_label(); TCGv_i32 tmp = tcg_temp_new_i32(); @@ -2318,6 +2353,7 @@ static void disas_xtensa_insn(DisasContext *dc) case 12: /*SSIUf*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); gen_window_check1(dc, RRI8_S); + gen_check_cpenable(dc, 0); { TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); @@ -2833,6 +2869,8 @@ static void gen_intermediate_code_internal( dc.ccount_delta = 0; dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; + dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + XTENSA_TBFLAG_CPENABLE_SHIFT; init_litbase(&dc); init_sar_tracker(&dc);