From patchwork Wed Sep 19 00:23:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 184894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 280AC2C0094 for ; Wed, 19 Sep 2012 10:51:21 +1000 (EST) Received: from localhost ([::1]:40024 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE86G-0002dt-6N for incoming@patchwork.ozlabs.org; Tue, 18 Sep 2012 20:25:08 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE85Y-0000Sw-OY for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TE85W-00055O-VO for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:24 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:64878) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE85W-00051u-Me for qemu-devel@nongnu.org; Tue, 18 Sep 2012 20:24:22 -0400 Received: by mail-lb0-f173.google.com with SMTP id gm13so378744lbb.4 for ; Tue, 18 Sep 2012 17:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=m89m8qxgYvYSEG80sgjjtIalRII9O3DJ/SCCYgK4H1U=; b=hBrJowndY3yONaXk9wDM6297PkE6bXG0WRmCsr+6vli7pdPlohdqQqL5Yxc3hv4jFn pFrmmG9lUn0kKrUguWaF8DqHwoNE/Fnc/utBLO2AZBO8qFyQj0HXcDLVEPXmKCJZ2zuS j+GaYXpxZZqAvuQ0YZqTMmTscbDWNJ7bPCT9rIL7+BBKQsQa6xIbZalsSo4N0iM2bSpa EIFMJNU7lUiveVwDbzwgwFz+AsP+0qHd4xjyuLF1X8VwjiDyMRlfVLkIaVqn66Y/0REh saMSMvO+k2pLKeRjMVVPPgZehhpe1JBKfApnXtgUCoBKc0axDEeazbHPAv+RoVxwc3QG oDPA== Received: by 10.112.86.232 with SMTP id s8mr439991lbz.117.1348014262289; Tue, 18 Sep 2012 17:24:22 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id hh10sm236651lab.10.2012.09.18.17.24.20 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Sep 2012 17:24:21 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 19 Sep 2012 04:23:58 +0400 Message-Id: <1348014239-6233-10-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1348014239-6233-1-git-send-email-jcmvbkbc@gmail.com> References: <1348014239-6233-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.217.173 Cc: Blue Swirl , Peter Maydell , Max Filippov Subject: [Qemu-devel] [PATCH v3 09/10] target-xtensa: implement FP1 group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These are comparison and conditional move opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov --- target-xtensa/helper.h | 8 ++++ target-xtensa/op_helper.c | 47 ++++++++++++++++++++++++++ target-xtensa/translate.c | 81 ++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 135 insertions(+), 1 deletions(-) diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 9557347..4cc0088 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -49,4 +49,12 @@ DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) DEF_HELPER_3(itof, f32, env, i32, i32) DEF_HELPER_3(uitof, f32, env, i32, i32) +DEF_HELPER_4(un_s, void, env, i32, f32, f32) +DEF_HELPER_4(oeq_s, void, env, i32, f32, f32) +DEF_HELPER_4(ueq_s, void, env, i32, f32, f32) +DEF_HELPER_4(olt_s, void, env, i32, f32, f32) +DEF_HELPER_4(ult_s, void, env, i32, f32, f32) +DEF_HELPER_4(ole_s, void, env, i32, f32, f32) +DEF_HELPER_4(ule_s, void, env, i32, f32, f32) + #include "def-helper.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 5cf9c02..ae0c099 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -858,3 +858,50 @@ float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) return float32_scalbn(uint32_to_float32(v, &env->fp_status), (int32_t)scale, &env->fp_status); } + +static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) +{ + if (v) { + env->sregs[BR] |= br; + } else { + env->sregs[BR] &= ~br; + } +} + +void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); +} + +void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); +} + +void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + int v = float32_compare_quiet(a, b, &env->fp_status); + set_br(env, v == float_relation_equal || v == float_relation_unordered, br); +} + +void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); +} + +void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + int v = float32_compare_quiet(a, b, &env->fp_status); + set_br(env, v == float_relation_less || v == float_relation_unordered, br); +} + +void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_le_quiet(a, b, &env->fp_status), br); +} + +void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + int v = float32_compare_quiet(a, b, &env->fp_status); + set_br(env, v != float_relation_greater, br); +} diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index fabde4f..652f9bb 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2001,7 +2001,86 @@ static void disas_xtensa_insn(DisasContext *dc) case 11: /*FP1*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - TBD(); + +#define gen_compare(rel, br, a, b) \ + do { \ + TCGv_i32 bit = tcg_const_i32(1 << br); \ + \ + gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ + tcg_temp_free(bit); \ + } while (0) + + switch (OP2) { + case 1: /*UN.Sf*/ + gen_compare(un_s, RRR_R, RRR_S, RRR_T); + break; + + case 2: /*OEQ.Sf*/ + gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); + break; + + case 3: /*UEQ.Sf*/ + gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); + break; + + case 4: /*OLT.Sf*/ + gen_compare(olt_s, RRR_R, RRR_S, RRR_T); + break; + + case 5: /*ULT.Sf*/ + gen_compare(ult_s, RRR_R, RRR_S, RRR_T); + break; + + case 6: /*OLE.Sf*/ + gen_compare(ole_s, RRR_R, RRR_S, RRR_T); + break; + + case 7: /*ULE.Sf*/ + gen_compare(ule_s, RRR_R, RRR_S, RRR_T); + break; + +#undef gen_compare + + case 8: /*MOVEQZ.Sf*/ + case 9: /*MOVNEZ.Sf*/ + case 10: /*MOVLTZ.Sf*/ + case 11: /*MOVGEZ.Sf*/ + gen_window_check1(dc, RRR_T); + { + static const TCGCond cond[] = { + TCG_COND_NE, + TCG_COND_EQ, + TCG_COND_GE, + TCG_COND_LT + }; + int label = gen_new_label(); + tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label); + tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); + gen_set_label(label); + } + break; + + case 12: /*MOVF.Sf*/ + case 13: /*MOVT.Sf*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + { + int label = gen_new_label(); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); + tcg_gen_brcondi_i32( + OP2 & 1 ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, label); + tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); + gen_set_label(label); + tcg_temp_free(tmp); + } + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; default: /*reserved*/