From patchwork Tue Sep 18 13:06:27 2012
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Subject: [AArch64] Implement ctz and clrsb standard patterns
From: Ian Bolton <ian.bolton@arm.com>
X-Patchwork-Id: 184710
Message-Id: <000501cd959e$6a2121a0$3e6364e0$@bolton@arm.com>
To: "Ian Bolton" <Ian.Bolton@arm.com>,
 "'Andreas Schwab'" <schwab@linux-m68k.org>
Cc: <gcc-patches@gcc.gnu.org>
Date: Tue, 18 Sep 2012 14:06:27 +0100

> > > diff --git a/gcc/config/aarch64/aarch64.md
> > b/gcc/config/aarch64/aarch64.md
> > > index 33815ff..5278957 100644
> > > --- a/gcc/config/aarch64/aarch64.md
> > > +++ b/gcc/config/aarch64/aarch64.md
> > > @@ -153,6 +153,8 @@
> > >      (UNSPEC_CMTST	 83) ; Used in aarch64-simd.md.
> > >      (UNSPEC_FMAX	 83) ; Used in aarch64-simd.md.
> > >      (UNSPEC_FMIN	 84) ; Used in aarch64-simd.md.
> > > +    (UNSPEC_CLS		 85) ; Used in aarch64-simd.md.
> > > +    (UNSPEC_RBIT	 86) ; Used in aarch64-simd.md.
> >
> > The comment doesn't appear to be true.
> >
> 
> Fair point!  I will fix that.
> 

New patch with comment fixed is attached.

Now good to commit to aarch64-branch and aarch64-4.7-branch?

Cheers,
Ian


diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 5d121fa..abf96c5 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -703,6 +703,8 @@ do {									     \
 
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+  ((VALUE) = ((MODE) == SImode ? 32 : 64), 2)
 
 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 33815ff..5278957 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -153,6 +153,8 @@
     (UNSPEC_CMTST	 83) ; Used in aarch64-simd.md.
     (UNSPEC_FMAX	 83) ; Used in aarch64-simd.md.
     (UNSPEC_FMIN	 84) ; Used in aarch64-simd.md.
+    (UNSPEC_CLS		 85) ; Used in aarch64.md.
+    (UNSPEC_RBIT	 86) ; Used in aarch64.md.
   ]
 )
 
@@ -2128,6 +2130,33 @@
   [(set_attr "v8type" "clz")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "clrsb<mode>2"
+  [(set (match_operand:GPI 0 "register_operand" "=r")
+	(unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))]
+  ""
+  "cls\\t%<w>0, %<w>1"
+  [(set_attr "v8type" "clz")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "rbit<mode>2"
+  [(set (match_operand:GPI 0 "register_operand" "=r")
+	(unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_RBIT))]
+  ""
+  "rbit\\t%<w>0, %<w>1"
+  [(set_attr "v8type" "rbit")
+   (set_attr "mode" "<MODE>")])
+
+(define_expand "ctz<mode>2"
+  [(match_operand:GPI 0 "register_operand")
+   (match_operand:GPI 1 "register_operand")]
+  ""
+  {
+    emit_insn (gen_rbit<mode>2 (operands[0], operands[1]));
+    emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+    DONE;
+  }
+)
+
 (define_insn "*and<mode>3nr_compare0"
   [(set (reg:CC CC_REGNUM)
 	(compare:CC
diff --git a/gcc/testsuite/gcc.target/aarch64/clrsb.c b/gcc/testsuite/gcc.target/aarch64/clrsb.c
new file mode 100644
index 0000000..a75dfa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clrsb.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest(unsigned int x)
+{
+	return __builtin_clrsb(x);
+}
+
+/* { dg-final { scan-assembler "cls\tw" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/clz.c b/gcc/testsuite/gcc.target/aarch64/clz.c
new file mode 100644
index 0000000..66e2d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/clz.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest(unsigned int x)
+{
+	return __builtin_clz(x);
+}
+
+/* { dg-final { scan-assembler "clz\tw" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ctz.c b/gcc/testsuite/gcc.target/aarch64/ctz.c
new file mode 100644
index 0000000..15a2473
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ctz.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest(unsigned int x)
+{
+  return __builtin_ctz(x);
+}
+
+/* { dg-final { scan-assembler "rbit\tw" } } */
+/* { dg-final { scan-assembler "clz\tw" } } */
+