From patchwork Tue Sep 18 08:20:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?5rmb5oyv5rOi?= X-Patchwork-Id: 184653 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7C5D02C0083 for ; Tue, 18 Sep 2012 18:24:52 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TDt3G-0004E3-Vk; Tue, 18 Sep 2012 08:21:03 +0000 Received: from mail-vc0-f177.google.com ([209.85.220.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TDt3D-0004Da-UI for linux-arm-kernel@lists.infradead.org; Tue, 18 Sep 2012 08:21:00 +0000 Received: by vcqp16 with SMTP id p16so1946969vcq.36 for ; Tue, 18 Sep 2012 01:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=yFV3YylC9f4cEhZOFu/ilryu5B4CyX2bF+0a5np+SHA=; b=e4GmQau1iVT5K4DAS3wXOEV/e7s09FPdeVSwKjf2fzcsbf5n/GFGRJ18cSp5oNZzmh ZGCXIQUqCtJ7z9/s23bLTMjLxHCFRK0Z3NQrnPW9YE5Ojz95B0NJJ3jkKscwh4M/OuJG oZAJU/NsVthttcnQlSrHgQyBf8zGZe7kgURh67cMcsXTSgCQALnlPNveF8DMZfqNDIvl FiICY3WtbWFncnalOOGGAczZQ2RNLPsfcqZ++Sr+OC015zlDGiSioxZ511iQ7w7jwoCf gzfcFNDzvJ426PSp7BosRaxhVV3qSCks9ucX7IbMkdcVuLkrTHiKZMGmFmB9XyNyhm1a rpiQ== MIME-Version: 1.0 Received: by 10.58.155.167 with SMTP id vx7mr9416532veb.24.1347956458589; Tue, 18 Sep 2012 01:20:58 -0700 (PDT) Received: by 10.221.1.84 with HTTP; Tue, 18 Sep 2012 01:20:58 -0700 (PDT) In-Reply-To: References: Date: Tue, 18 Sep 2012 16:20:58 +0800 Message-ID: Subject: Re: ARM: smp: why don't eliminate warning "Unknown IPI message 0x1"? From: "steve.zhan" To: linux-arm-kernel@lists.infradead.org X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (zhanzhenbo[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: rmk+kernel@arm.linux.org.uk, "will.deacon" , santosh.shilimkar@ti.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Below is the whole of the patch. while (time_before(jiffies, timeout)) { @@ -137,6 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) udelay(10); } + smp_send_wakeup_ipi_end(cpu, 0); /* * now the secondary core is starting up let it run its 2012/9/18, 湛振波 : > Russell King want people to move to SGI0 for this, so that we can have > SGI1-N > as the proper IPIs, but now we can't do this, maybe we must wait for > so many years. > But, Do you think we can use a another way to resolve this problem, > because this warning message will oftenly appeare in products. > > We can't assume the fixed IPI number that can wakeup secondary cores. > "I'd much rather see platforms deciding whether they need to use SGI1 > or whether they can switch to SGI0 instead." > > Just give one ugly idea. I have modify this for example in msm platform. > Pls check the attached git diff patch Or below lines and give your > suggestions > diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index ea73045..8605400 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -495,11 +496,28 @@ asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) handle_IPI(ipinr, regs); } +static int ipi_wakeup_nr[NR_CPUS]; + +void smp_send_wakeup_ipi_begin(unsigned int cpu, unsigned int irq) +{ + ipi_wakeup_nr[cpu] = irq + 1; + gic_raise_softirq(cpumask_of(cpu),irq); +} + +void smp_send_wakeup_ipi_end(unsigned int cpu, unsigned int irq) +{ + BUG_ON(ipi_wakeup_nr[cpu] != irq + 1); + ipi_wakeup_nr[cpu] = 0; +} + void handle_IPI(int ipinr, struct pt_regs *regs) { unsigned int cpu = smp_processor_id(); struct pt_regs *old_regs = set_irq_regs(regs); + if (ipi_wakeup_nr[cpu] == ipinr + 1) + goto Exit; + if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI) __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]); @@ -537,6 +555,7 @@ void handle_IPI(int ipinr, struct pt_regs *regs) cpu, ipinr); break; } +Exit: set_irq_regs(old_regs); } diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index db0117e..ecc6add 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -127,7 +127,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - gic_raise_softirq(cpumask_of(cpu), 1); + smp_send_wakeup_ipi_begin(cpu, 0); timeout = jiffies + (1 * HZ);