From patchwork Tue Sep 18 02:11:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 184589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6C6282C0083 for ; Tue, 18 Sep 2012 12:34:37 +1000 (EST) Received: from localhost ([::1]:55108 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDnK1-0007vb-MB for incoming@patchwork.ozlabs.org; Mon, 17 Sep 2012 22:13:57 -0400 Received: from eggs.gnu.org ([208.118.235.92]:46028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDnJ3-0006KE-Nh for qemu-devel@nongnu.org; Mon, 17 Sep 2012 22:12:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDnJ2-0004dO-Ey for qemu-devel@nongnu.org; Mon, 17 Sep 2012 22:12:57 -0400 Received: from mail-ob0-f173.google.com ([209.85.214.173]:38380) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDnJ2-0004NA-A0 for qemu-devel@nongnu.org; Mon, 17 Sep 2012 22:12:56 -0400 Received: by mail-ob0-f173.google.com with SMTP id ta14so9259606obb.4 for ; Mon, 17 Sep 2012 19:12:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=CMaHgYWq/V0YGrXt6ewUBpBUbum8YBvNyqAJka+YF0c=; b=E7l59jyK4Pu3Wsib81WbLd7Ov0MJ1pAUatY7Hi1KLRtoyV4k8CuoTB4BbEo6Ze3cQY lc2/N/lyoumfS1qHU289DmJst80v+CwhAlSHO6v9lAAfB/SAM77Qj5Vsf/7wp9Ekj0ua 7F0Fbl6eaYhgg+e3AZJ0TVvbc34y74eqzEEOytw9Ep18E9C6a3mfTjuLl0YUkHdp0CPP 7qR0W1POzPSHfcCYBis9gQrVO6YHgNIsb9xZ0j4sE3+jL9vcDJFuoOXKA4r73yVOZ+NO isG2tTKhjljUQPEf93XovQoL650ZKVdk7r48z8uFb62JgSZnO4+YsaS6HqVaHXSROzyl 2ocA== Received: by 10.60.170.47 with SMTP id aj15mr13688675oec.29.1347934376065; Mon, 17 Sep 2012 19:12:56 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id x1sm10378762oef.8.2012.09.17.19.12.53 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 17 Sep 2012 19:12:55 -0700 (PDT) From: "Peter A. G. Crosthwaite" To: qemu-devel@nongnu.org, paul@codesourcery.com, edgar.iglesias@gmail.com, peter.maydell@linaro.org, stefanha@gmail.com Date: Tue, 18 Sep 2012 12:11:09 +1000 Message-Id: <2bf25cbe5b6e5d86b8c62c12260a7882e9e7e419.1347932427.git.peter.crosthwaite@petalogix.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQkKdfuwN9WCytGHHz8SV8jSO0amch2gJlvtSwFOeN7Da28ZTs4qvF+Z9iem50+uj4ZP/bBr X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.173 Cc: "Peter A. G. Crosthwaite" , i.mitsyanko@samsung.com Subject: [Qemu-devel] [PATCH v6 12/13] xilinx_zynq: Added SPI controllers + flashes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added the two SPI controllers to the zynq machine model. Attached two SPI flash devices to each controller. Signed-off-by: Peter A. G. Crosthwaite --- hw/xilinx_zynq.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 7e6c273..e273711 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -24,6 +24,9 @@ #include "flash.h" #include "blockdev.h" #include "loader.h" +#include "ssi.h" + +#define NUM_SPI_FLASHES 2 #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) @@ -46,6 +49,34 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } +static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *busdev; + SSIBus *spi; + int i; + + dev = qdev_create(NULL, "xilinx,spips"); + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, base_addr); + sysbus_connect_irq(busdev, 0, irq); + + spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); + + for (i = 0; i < NUM_SPI_FLASHES; ++i) { + qemu_irq cs_line; + + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", (char *)"n25q128"); + qdev_init_nofail(dev); + + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i+1, cs_line); + } + +} + static void zynq_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -113,6 +144,9 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, pic[n] = qdev_get_gpio_in(dev, n); } + zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]); + zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]); + sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);