From patchwork Tue Sep 18 02:11:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 184587 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 333BF2C007F for ; Tue, 18 Sep 2012 12:27:35 +1000 (EST) Received: from localhost ([::1]:50805 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDnIh-0005Zs-6Y for incoming@patchwork.ozlabs.org; Mon, 17 Sep 2012 22:12:35 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDnID-0004Fd-6s for qemu-devel@nongnu.org; Mon, 17 Sep 2012 22:12:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDnIB-0004P2-HE for qemu-devel@nongnu.org; Mon, 17 Sep 2012 22:12:05 -0400 Received: from mail-ob0-f173.google.com ([209.85.214.173]:38380) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDnIB-0004NA-Bp for qemu-devel@nongnu.org; Mon, 17 Sep 2012 22:12:03 -0400 Received: by mail-ob0-f173.google.com with SMTP id ta14so9259606obb.4 for ; Mon, 17 Sep 2012 19:12:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=8xHmY8D141P4pGxvqoNgg1Hca+ZAkY5/q9QDBX7P0xY=; b=Y3Q6rXpGt26M8YJZetLayvx9+7G59IEMXWeG9k37cMTHnkFWyVG74Y1JwBP+ojS8YR bLV0nf21goh91yPN+QsM+Zw429PUCG+HNTmZx1Co32X0p5FpWjBCCBxQqIyLryQLMTO7 TsvSxXasDgJuqhqbu/PZKbd7Ose4Cw8kAqnDWgB7ODtPhQt/pXgZBkXQkoV/cATYpN3q Lp1j2zc6RNJGQldN55Is0gbmXCQNM8FbL5ODGRb1v9pltETKi4WqbCut/wgc9w4/NVF4 Uxh8JSjOdvpzNW85tVFWHpdBWIOChdY3/l89IkdXB951FNWsK57+eR3XQ9j5pyhia7kr nz7w== Received: by 10.182.193.7 with SMTP id hk7mr13737421obc.30.1347934323185; Mon, 17 Sep 2012 19:12:03 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id x1sm10376002oef.8.2012.09.17.19.12.00 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 17 Sep 2012 19:12:02 -0700 (PDT) From: "Peter A. G. Crosthwaite" To: qemu-devel@nongnu.org, paul@codesourcery.com, edgar.iglesias@gmail.com, peter.maydell@linaro.org, stefanha@gmail.com Date: Tue, 18 Sep 2012 12:11:01 +1000 Message-Id: <10d733eb919c22c7f236c3b289896320978a3257.1347932427.git.peter.crosthwaite@petalogix.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQlYfooTB4KxLym+5qszhJkoEobn47bEnZ2umjwwu8u/QWK1lN2Cfkm3gUb3XsQXt4VRBatp X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.173 Cc: "Peter A. G. Crosthwaite" , i.mitsyanko@samsung.com Subject: [Qemu-devel] [PATCH v6 04/13] qdev: allow multiple qdev_init_gpio_in() calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Allow multiple qdev_init_gpio_in() calls for the one device. The first call will define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled with different handlers. Needed when two levels of the QOM class heirachy both define GPIO functionality, as a single GPIO handler with an index selecter is not possible. Signed-off-by: Peter A. G. Crosthwaite --- changed since v5: moved implementation to irq.c as per PMM review hw/irq.c | 17 ++++++++++++++--- hw/irq.h | 11 ++++++++++- hw/qdev.c | 6 +++--- 3 files changed, 27 insertions(+), 7 deletions(-) diff --git a/hw/irq.c b/hw/irq.c index d413a0b..cd17551 100644 --- a/hw/irq.c +++ b/hw/irq.c @@ -38,15 +38,20 @@ void qemu_set_irq(qemu_irq irq, int level) irq->handler(irq->opaque, irq->n, level); } -qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) +qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, + void *opaque, int n) { qemu_irq *s; struct IRQState *p; int i; - s = (qemu_irq *)g_malloc0(sizeof(qemu_irq) * n); + if (!old) { + n_old = 0; + } + s = old ? g_renew(qemu_irq, old, n + n_old) : + (qemu_irq *)g_new0(qemu_irq, n); p = (struct IRQState *)g_malloc0(sizeof(struct IRQState) * n); - for (i = 0; i < n; i++) { + for (i = n_old; i < n + n_old; i++) { p->handler = handler; p->opaque = opaque; p->n = i; @@ -56,6 +61,12 @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) return s; } +qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) +{ + return qemu_extend_irqs(NULL, 0, handler, opaque, n); +} + + void qemu_free_irqs(qemu_irq *s) { g_free(s[0]); diff --git a/hw/irq.h b/hw/irq.h index 56c55f0..e640c10 100644 --- a/hw/irq.h +++ b/hw/irq.h @@ -23,8 +23,17 @@ static inline void qemu_irq_pulse(qemu_irq irq) qemu_set_irq(irq, 0); } -/* Returns an array of N IRQs. */ +/* Returns an array of N IRQs. Each IRQ is assigned the argument handler and + * opaque data. + */ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n); + +/* Extends an Array of IRQs. Old IRQs have their handlers and opaque data + * preserved. New IRQs are assigned the argument handler and opaque data. + */ +qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, + void *opaque, int n); + void qemu_free_irqs(qemu_irq *s); /* Returns a new IRQ with opposite polarity. */ diff --git a/hw/qdev.c b/hw/qdev.c index b5a52ac..eea9eae 100644 --- a/hw/qdev.c +++ b/hw/qdev.c @@ -291,9 +291,9 @@ BusState *qdev_get_parent_bus(DeviceState *dev) void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n) { - assert(dev->num_gpio_in == 0); - dev->num_gpio_in = n; - dev->gpio_in = qemu_allocate_irqs(handler, dev, n); + dev->gpio_in = qemu_extend_irqs(dev->gpio_in, dev->num_gpio_in, handler, + dev, n); + dev->num_gpio_in += n; } void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n)