From patchwork Mon Sep 17 19:51:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 184526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 05F972C0085 for ; Tue, 18 Sep 2012 05:53:02 +1000 (EST) Comment: DKIM? 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Violators will be prosecuted; Mon, 17 Sep 2012 15:51:49 -0400 Received: from d03av06.boulder.ibm.com (d03av06.boulder.ibm.com [9.17.195.245]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q8HJpikp129862 for ; Mon, 17 Sep 2012 15:51:46 -0400 Received: from d03av06.boulder.ibm.com (loopback [127.0.0.1]) by d03av06.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q8HJr6md007258 for ; Mon, 17 Sep 2012 13:53:07 -0600 Received: from ibm-tiger.the-meissners.org ([9.33.48.180]) by d03av06.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q8HJr6Un007036; Mon, 17 Sep 2012 13:53:06 -0600 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 4F81641536; Mon, 17 Sep 2012 15:51:32 -0400 (EDT) Date: Mon, 17 Sep 2012 15:51:32 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, bergner@vnet.ibm.com, segher@kernel.crashing.org, iain@codesourcery.com, andreast-list@fgznet.ch Subject: Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch Message-ID: <20120917195131.GA22648@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, bergner@vnet.ibm.com, segher@kernel.crashing.org, iain@codesourcery.com, andreast-list@fgznet.ch References: <20120912224303.GA19348@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20120912224303.GA19348@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) x-cbid: 12091719-7182-0000-0000-000002A52FB8 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch has support for all of the additonal cleanups I mentioned in the first patch that I hadn't gotten to. At this point, I am not planning any more enhancements to the patch, and I would like to check it in. On my 64-bit powerpc system, there are 36 options in the main ISA flags fields, 23 options in the miscellaneous flags fields, and 8 options in the debug flag fields. I believe it answers the problems Ian had. I changed all of the debugging fprintf's to use HOST_WIDE_INT_PRINT_HEX to print the numeric value of the flags fields, and I changed the #ifdef TARGET_ to #ifdef OPTION_. It builds and bootstraps fine on my powerpc64 linux system and there were no regressions. It is ok to install? 2012-09-14 Michael Meissner * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Move all switches that set target_flags to set rs6000_isa_flags, and make it HOST_WIDE_INT. Make SPE/paired floating point ISA bits once again. Move other switches that were previously separate variables back as option bits, and add rs6000_misc_flags and rs6000_debug_flags. Save/restore new option words. Change MASK_ to OPTION_MASK_. Add TARGET_ maps for OPTION_. Move -mdebug=xxx handling to rs6000.opt file. Add rs6000-cpus.def as rs6000.o dependency. Use rs6000_isa_options for all builtins. Print more debug output for -mdebug=reg. Move masks for different cpu levels to rs6000-cpus.def. Move branch hint, align branch targets, schedule groups to tune flags in rs6000-cpus.def. Turn off VSX if the assembler doesn't support Altivec. * config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Likewise. * config/rs6000/eabi.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabispe.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Likewise. * config/rs6000/darwin64.h (TARGET_DEFAULT): Likewise. * config/rs6000/default64.h (TARGET_DEFAULT): Likewise. * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Likewise. * config/rs6000/darwin.h (TARGET_DEFAULT): Likewise. * config/rs6000/sysv4le.h (TARGET_DEFAULT): Likewis.e * config/rs6000/xfpu.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabispe.h (TARGET_DEFAULT): Likewise. * config/rs6000/vxworks.h (TARGET_DEFAULT): Likewise. * config/rs6000/rs6000.opt (most options): Likewise. * config/rs6000/sysv4.opt (most options): Likewise. * config/rs6000/darwin64.opt (most options): Likewise. * config/rs6000/aix64.opt (most options): Likewise. * config/rs6000/linux64.opt (-mprofile-kernel): Likewise. * config/rs6000/476.opt (-mpreserve-link-stack): Likewise. * config/rs6000/476.h (TARGET_LINK_STACK): Likewise. * config/rs6000/secureplt.h (OPTION_MASK_DEFAULT_SECURE_PLT): Likewise. (SET_TARGET_LINK_STACK): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * config/rs6000/rs6000-builtin.def (all BU_* macros): Likewise. * config/rs6000/linux64.h (DEFAULT_ARCH64_P): Likewise. (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/rs6000.c (struct builtin_description): Likewise. (rs6000_target_modify_macros_ptr): Likewise. (struct processor_costs): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (struct rs6000_ptt): Likewise. (DEBUG_FMT_LX): Likewise. (DEBUG_FMT_LX2): Likewise. (rs6000_debug_reg_global): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_builtin_mask_calculate): Likewise. (rs6000_operand_tuning_flag): Likewise. (rs6000_option_override_internal): Likewise. (altivec_expand_dst_builtin): Likewise. (paired_expand_builtin): Likewise. (bdesc_2arg_spe): Likewise. (spe_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_init_builtins): Likewise. (rs6000_builtin_decl): Likewise. (rs0600_common_init_builtins): Likewise. (rs6000_handle_altivec_attribute): Likewise. (rs6000_darwin_file_start): Likewise. (rs6000_final_prescan_insn): Likewise. (rs6000_opt_masks): Likewise. (rs6000_opt_vars): Likewise. (rs6000_misc_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_resotre): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_print_isa_options): Likewise. (rs6000_print_isa_vars): Likewise. (rs6000_can_inline_p): Likewise. * config/rs6000/750cl.h (TARGET_PAIRED_FLOAT): Likewise. (TARGET_USES_PAIRED_FLOAT): Likewise. * config/rs6000/rs6000.h (TARGET_*): Likewise. (MASK_DEBUG_*): Likewise. (ALL_DEBUG_MASKS): Likewise. (RS6000_BTM_*): Likewise. * config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * config/rs6000/rs6000-cpus.def (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWER_BASE_MASK): Likewise. (POWER4_ISA_MASK): Likewise. (POWER4_TUNE_MASK): Likewsie. (POWER5_ISA_MASK): Likewise. (POWER5P_ISA_MASK): Likewise. (POWER5_TUNE_MASK): Likewsie. (POWER6_ISA_MASK): Likewise. (POWER6X_ISA_MASK): Likewise. (POWER6_TUNE_MASK): Likewsie. (POWER7_ISA_MASK): Likewise. (POWER7_TUNE_MASK): Likewsie. (MASK_*): Likewise. (476 cpu): Likewise. (476fp cpu): Likewise. (8540 cpu): Likewise. (8548 cpu): Likewise. (a2 cpu): Likewise. (e500mc cpu): Likewise. (e500mc64 cpu): Likewise. (e5500 cpu): Likewise. (e6500 cpu): Likewise. (970 cpu): Likewise. (cell cpu): Likewise. (G5 cpu): Likewise. (power4 cpu): Likewise. (power5 cpu): Likewise. (power5+ cpu): Likewise. (power6 cpu): Likewise. (power6x cpu): Likewise. (power7 cpu): Likewise. * config/rs6000/e500.h (TARGET_USES_SPE): Likewise. (TARGET_SPE): Likewise. * config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. * config/rs6000/rs6000-protos.h (rs6000_builtin_mask_calculate): Likewise. (rs6000_target_modify_macros): Likewise. (rs6000_target_modify_macros_ptr): Likewise. * config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): Likewise. * config/rs6000/rs6000.md (cell microcode insns): Likewise. Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 191266) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -74,7 +74,6 @@ rs6000_handle_option (struct gcc_options location_t loc) { enum fpu_type_t fpu_type = FPU_NONE; - char *p, *q; size_t code = decoded->opt_index; const char *arg = decoded->arg; int value = decoded->value; @@ -82,23 +81,25 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; - opts->x_TARGET_NO_FP_IN_TOC = 0; - opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); + opts_set->x_rs6000_misc_flags |= (OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +108,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,63 +119,17 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: if (value == 1) { - opts->x_TARGET_NO_FP_IN_TOC = 0; - opts->x_TARGET_NO_SUM_IN_TOC = 0; - } - break; - - case OPT_mpowerpc_gpopt: - case OPT_mpowerpc_gfxopt: - break; - - case OPT_mdebug_: - p = ASTRDUP (arg); - opts->x_rs6000_debug = 0; - - while ((q = strtok (p, ",")) != NULL) - { - unsigned mask = 0; - bool invert; - - p = NULL; - if (*q == '!') - { - invert = true; - q++; - } - else - invert = false; - - if (! strcmp (q, "all")) - mask = MASK_DEBUG_ALL; - else if (! strcmp (q, "stack")) - mask = MASK_DEBUG_STACK; - else if (! strcmp (q, "arg")) - mask = MASK_DEBUG_ARG; - else if (! strcmp (q, "reg")) - mask = MASK_DEBUG_REG; - else if (! strcmp (q, "addr")) - mask = MASK_DEBUG_ADDR; - else if (! strcmp (q, "cost")) - mask = MASK_DEBUG_COST; - else if (! strcmp (q, "target")) - mask = MASK_DEBUG_TARGET; - else if (! strcmp (q, "builtin")) - mask = MASK_DEBUG_BUILTIN; - else - error_at (loc, "unknown -mdebug-%s switch", q); - - if (invert) - opts->x_rs6000_debug &= ~mask; - else - opts->x_rs6000_debug |= mask; + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); + opts_set->x_rs6000_misc_flags |= (OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); } break; @@ -181,23 +137,27 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; - opts->x_TARGET_NO_FP_IN_TOC = 1; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; + opts_set->x_rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; } break; case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts->x_TARGET_NO_FP_IN_TOC = 1; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; + opts_set->x_rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -207,9 +167,11 @@ rs6000_handle_option (struct gcc_options opts->x_rs6000_spe_abi = 0; break; +#if TARGET_USES_SPE case OPT_mabi_spe: opts->x_rs6000_altivec_abi = 0; break; +#endif case OPT_mlong_double_: if (value != 64 && value != 128) @@ -227,15 +189,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,9 +221,12 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; - opts->x_rs6000_xilinx_fpu = 1; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; +#if TARGET_USES_XILINX_FPU + opts->x_rs6000_isa_flags |= OPTION_MASK_XILINX_FPU; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_XILINX_FPU; +#endif if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL) @@ -272,8 +237,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -281,6 +246,31 @@ rs6000_handle_option (struct gcc_options case OPT_mrecip: opts->x_rs6000_recip_name = (value) ? "default" : "none"; break; + + /* Note, the compiler must be configured explicitly for spe, paired, and + xilinx support. */ +#if !TARGET_USES_SPE + case OPT_mabi_no_spe: + case OPT_mabi_spe: + error ("not configured for SPE ABI"); + break; + + case OPT_mspe: + error ("not configured for SPE instruction set"); + break; +#endif + +#if !TARGET_USES_PAIRED_FLOAT + case OPT_mpaired: + error ("not configured for the 750CL paired floating point"); + break; +#endif + +#if !TARGET_USES_XILINX_FPU + case OPT_mxilinx_fpu: + error ("not configured for the xilinx_fpu"); + break; +#endif } return true; } @@ -297,8 +287,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 191266) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/476.opt =================================================================== --- gcc/config/rs6000/476.opt (revision 191266) +++ gcc/config/rs6000/476.opt (working copy) @@ -20,5 +20,5 @@ ; . mpreserve-link-stack -Target Var(rs6000_link_stack) Init(-1) Save +Target Report InverseMask(NO_LINK_STACK) Var(rs6000_misc_flags) Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl insns used for GOT accesses Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 191266) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/eabi.h =================================================================== --- gcc/config/rs6000/eabi.h (revision 191266) +++ gcc/config/rs6000/eabi.h (working copy) @@ -21,7 +21,7 @@ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_EABI +#define TARGET_DEFAULT OPTION_MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 191266) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/secureplt.h =================================================================== --- gcc/config/rs6000/secureplt.h (revision 191266) +++ gcc/config/rs6000/secureplt.h (working copy) @@ -18,3 +18,5 @@ along with GCC; see the file COPYING3. . */ #define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt" + +#define OPTION_MASK_DEFAULT_SECURE_PLT OPTION_MASK_SECURE_PLT Index: gcc/config/rs6000/linuxspe.h =================================================================== --- gcc/config/rs6000/linuxspe.h (revision 191266) +++ gcc/config/rs6000/linuxspe.h (working copy) @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_STRICT_ALIGN +#define TARGET_DEFAULT OPTION_MASK_STRICT_ALIGN #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" Index: gcc/config/rs6000/eabialtivec.h =================================================================== --- gcc/config/rs6000/eabialtivec.h (revision 191266) +++ gcc/config/rs6000/eabialtivec.h (working copy) @@ -21,7 +21,7 @@ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_ALTIVEC) #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 Index: gcc/config/rs6000/476.h =================================================================== --- gcc/config/rs6000/476.h (revision 191266) +++ gcc/config/rs6000/476.h (working copy) @@ -23,10 +23,18 @@ . */ #undef TARGET_LINK_STACK -#define TARGET_LINK_STACK (rs6000_link_stack) +#define TARGET_LINK_STACK (! OPTION_NO_LINK_STACK) #undef SET_TARGET_LINK_STACK -#define SET_TARGET_LINK_STACK(X) do { TARGET_LINK_STACK = (X); } while (0) +#define SET_TARGET_LINK_STACK(X) \ +do \ + { \ + if (X) \ + rs6000_misc_flags &= ~OPTION_MASK_NO_LINK_STACK; \ + else \ + rs6000_misc_flags |= OPTION_MASK_NO_LINK_STACK; \ + } \ +while (0) #undef TARGET_ASM_CODE_END #define TARGET_ASM_CODE_END rs6000_code_end Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 191266) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/default64.h =================================================================== --- gcc/config/rs6000/default64.h (revision 191266) +++ gcc/config/rs6000/default64.h (working copy) @@ -19,4 +19,5 @@ along with GCC; see the file COPYING3. . */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_64BIT) Index: gcc/config/rs6000/darwin64.h =================================================================== --- gcc/config/rs6000/darwin64.h (revision 191266) +++ gcc/config/rs6000/darwin64.h (working copy) @@ -19,8 +19,8 @@ . */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_POWERPC64 | OPTION_MASK_64BIT \ + | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 191266) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000-builtin.def =================================================================== --- gcc/config/rs6000/rs6000-builtin.def (revision 191266) +++ gcc/config/rs6000/rs6000-builtin.def (working copy) @@ -90,7 +90,7 @@ #define BU_ALTIVEC_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -98,7 +98,7 @@ #define BU_ALTIVEC_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -106,7 +106,7 @@ #define BU_ALTIVEC_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -114,7 +114,7 @@ #define BU_ALTIVEC_A(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_A (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -122,7 +122,7 @@ #define BU_ALTIVEC_D(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_D (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_DST), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -130,7 +130,7 @@ #define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -138,7 +138,7 @@ #define BU_ALTIVEC_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -146,8 +146,8 @@ #define BU_ALTIVEC_C(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - (RS6000_BTM_ALTIVEC /* MASK */ \ - | RS6000_BTM_CELL), \ + (OPTION_MASK_ALTIVEC /* MASK */ \ + | OPTION_MASK_CELL_BUILTIN), \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -156,7 +156,7 @@ #define BU_ALTIVEC_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -164,7 +164,7 @@ #define BU_ALTIVEC_OVERLOAD_2(ENUM, NAME) \ RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_nothing) /* ICODE */ @@ -172,7 +172,7 @@ #define BU_ALTIVEC_OVERLOAD_3(ENUM, NAME) \ RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -180,7 +180,7 @@ #define BU_ALTIVEC_OVERLOAD_A(ENUM, NAME) \ RS6000_BUILTIN_A (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_nothing) /* ICODE */ @@ -188,7 +188,7 @@ #define BU_ALTIVEC_OVERLOAD_D(ENUM, NAME) \ RS6000_BUILTIN_D (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_DST), \ CODE_FOR_nothing) /* ICODE */ @@ -196,7 +196,7 @@ #define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_nothing) /* ICODE */ @@ -204,7 +204,7 @@ #define BU_ALTIVEC_OVERLOAD_X(ENUM, NAME) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -213,7 +213,7 @@ #define BU_VSX_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -221,7 +221,7 @@ #define BU_VSX_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -229,7 +229,7 @@ #define BU_VSX_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -237,7 +237,7 @@ #define BU_VSX_A(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_A (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -245,7 +245,7 @@ #define BU_VSX_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -253,7 +253,7 @@ #define BU_VSX_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -262,7 +262,7 @@ #define BU_VSX_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -270,7 +270,7 @@ #define BU_VSX_OVERLOAD_2(ENUM, NAME) \ RS6000_BUILTIN_2 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_nothing) /* ICODE */ @@ -278,7 +278,7 @@ #define BU_VSX_OVERLOAD_3(ENUM, NAME) \ RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -288,7 +288,7 @@ #define BU_VSX_OVERLOAD_3V(ENUM, NAME) \ RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -296,7 +296,7 @@ #define BU_VSX_OVERLOAD_X(ENUM, NAME) \ RS6000_BUILTIN_X (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -305,7 +305,7 @@ #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -313,7 +313,7 @@ #define BU_SPE_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -321,7 +321,7 @@ #define BU_SPE_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -329,7 +329,7 @@ #define BU_SPE_E(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_EVSEL), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -337,7 +337,7 @@ #define BU_SPE_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -345,7 +345,7 @@ #define BU_SPE_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -354,7 +354,7 @@ #define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -362,7 +362,7 @@ #define BU_PAIRED_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -370,7 +370,7 @@ #define BU_PAIRED_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -378,7 +378,7 @@ #define BU_PAIRED_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_Q (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -386,7 +386,7 @@ #define BU_PAIRED_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -1413,22 +1413,22 @@ BU_SPE_X (MTSPEFSCR, "mtspefscr", /* Power7 builtins, that aren't VSX instructions. */ -BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD, +BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", OPTION_MASK_POPCNTD, RS6000_BTC_CONST) /* Miscellaneous builtins. */ -BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", RS6000_BTM_FRE, +BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", OPTION_MASK_POPCNTB, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", RS6000_BTM_FRES, - RS6000_BTC_FP) +BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", + OPTION_MASK_PPC_GFXOPT, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE, - RS6000_BTC_FP) +BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", + OPTION_MASK_PPC_GFXOPT, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, +BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", OPTION_MASK_POPCNTB, RS6000_BTC_FP) /* Darwin CfString builtin. */ -BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, +BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", 0, RS6000_BTC_MISC) Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 191266) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -41,9 +41,8 @@ where TOGGLE is either 0 or 1. - rs6000_default_long_calls is set to the value of TOGGLE, changing - whether or not new function declarations receive a longcall - attribute by default. */ + TARGET_LONG_CALLS is set to the value of TOGGLE, changing whether or not new + function declarations receive a longcall attribute by default. */ #define SYNTAX_ERROR(gmsgid) do { \ warning (OPT_Wpragmas, gmsgid); \ @@ -72,7 +71,10 @@ rs6000_pragma_longcall (cpp_reader *pfil if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of #pragma longcall"); - rs6000_default_long_calls = (n == integer_one_node); + if (n == integer_one_node) + rs6000_isa_flags |= OPTION_MASK_LONG_CALLS; + else + rs6000_isa_flags &= ~OPTION_MASK_LONG_CALLS; } /* Handle defining many CPP flags based on TARGET_xxx. As a general @@ -285,38 +287,38 @@ rs6000_define_or_undefine_macro (bool de have both the target flags and the builtin flags as arguments. */ void -rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n", + fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%lx)\n", (define_p) ? "define" : "undef", - (unsigned) flags, bu_mask); + (unsigned long) flags); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -326,15 +328,15 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ - if ((bu_mask & RS6000_BTM_SPE) != 0) + if ((flags & OPTION_MASK_SPE) != 0) rs6000_define_or_undefine_macro (define_p, "__SPE__"); - if ((bu_mask & RS6000_BTM_PAIRED) != 0) + if ((flags & OPTION_MASK_PAIRED_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "__PAIRED__"); - if ((bu_mask & RS6000_BTM_CELL) != 0) + if ((flags & OPTION_MASK_CELL_BUILTIN) != 0) rs6000_define_or_undefine_macro (define_p, "__PPU__"); } @@ -342,8 +344,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, - rs6000_builtin_mask_calculate ()); + rs6000_target_modify_macros (true, rs6000_isa_flags); if (TARGET_FRE) builtin_define ("__RECIP__"); @@ -463,7 +464,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi builtin_define ("__NO_FPRS__"); /* Generate defines for Xilinx FPU. */ - if (rs6000_xilinx_fpu) + if (TARGET_XILINX_FPU) { builtin_define ("_XFPU"); if (rs6000_single_float && ! rs6000_double_float) Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 191266) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,39 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + +;; Miscellaneous flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_misc_flags = TARGET_MISC_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_misc_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_misc_flags_explicit + +;; Debug flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_debug_flags = TARGET_DEBUG_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_debug_flags + +;; Debug flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_debug_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -80,161 +113,161 @@ unsigned int rs6000_recip_control ;; Mask of what builtin functions are allowed TargetVariable -unsigned int rs6000_builtin_mask +HOST_WIDE_INT rs6000_builtin_mask ;; Debug flags TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction +mno-friz +Target Report RejectNegative Mask(NO_FRIZ) Var(rs6000_isa_flags) +Under -ffast-math, do not generate a FRIZ instruction for (double)(long long) conversions + mfriz -Target Report Var(TARGET_FRIZ) Init(-1) Save +Target Report RejectNegative InverseMask(NO_FRIZ, FRIZ) Var(rs6000_isa_flags) Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions +mcell-builtins +Target Undocumented Report Mask(CELL_BUILTIN) Var(rs6000_isa_flags) +; Enable cell builtins + mveclibabi= Target RejectNegative Joined Var(rs6000_veclibabi_name) Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double -Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) +Target Report Undocumented Mask(VSX_SCALAR_DOUBLE) Var(rs6000_misc_flags) ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) mvsx-scalar-memory -Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) +Target Report Undocumented Mask(VSX_SCALAR_MEMORY) Var(rs6000_misc_flags) ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) mvsx-align-128 -Target Undocumented Report Var(TARGET_VSX_ALIGN_128) +Target Report Undocumented Mask(VSX_ALIGN_128) Var(rs6000_misc_flags) ; If -mvsx, set alignment to 128 bits instead of 32/64 mallow-movmisalign -Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) +Target Report Undocumented Mask(ALLOW_MOVMISALIGN) Var(rs6000_misc_flags) ; Allow/disallow the movmisalign in DF/DI vectors -mallow-df-permute -Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) -; Allow/disallow permutation of DF/DI vectors - msched-groups -Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) +Target Undocumented Report Mask(SCHED_GROUPS) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_sched_groups is set malways-hint -Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) +Target Undocumented Report InverseMask(NO_HINT) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_always_hint is set malign-branch-targets -Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) +Target Undocumented Report Mask(ALIGN_BRANCH_TARGETS) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_align_branch_targets is set mvectorize-builtins -Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) +Target Undocumented Report Mask(VECTORIZE_BUILTINS) Var(rs6000_misc_flags) ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base -Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) +Target Report Mask(SINGLE_PIC_BASE) Var(rs6000_misc_flags) Do not load the PIC register in function prologues mavoid-indexed-addresses -Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save +Target Report Mask(AVOID_XFORM) Var(rs6000_isa_flags) Avoid generation of indexed load/store instructions when possible mtls-markers -Target Report Var(tls_markers) Init(1) Save +Target Report Mask(TLS_MARKERS) Var(rs6000_misc_flags) Mark __tls_get_addr calls with argument info msched-epilog -Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save +Target Report Undocumented Mask(SCHED_PROLOG) Var(rs6000_misc_flags) msched-prolog -Target Report Var(TARGET_SCHED_PROLOG) Save +Target Report Mask(SCHED_PROLOG) Var(rs6000_misc_flags) Schedule the start and end of the procedure maix-struct-return @@ -246,7 +279,7 @@ Target Report RejectNegative Var(aix_str Return small structures in registers (SVR4 default) mxl-compat -Target Report Var(TARGET_XL_COMPAT) Save +Target Report Mask(XL_COMPAT) Var(rs6000_misc_flags) Conform more closely to IBM XLC semantics mrecip @@ -258,24 +291,16 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. -mno-fp-in-toc -Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save -Do not place floating point constants in TOC - mfp-in-toc -Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save -Place floating point constants in TOC - -mno-sum-in-toc -Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save -Do not place symbol+offset constants in TOC +Target Report InverseMask(NO_FP_IN_TOC) Var(rs6000_misc_flags) +Place/do not place floating point constants in TOC msum-in-toc -Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save -Place symbol+offset constants in TOC +Target Report InverseMask(NO_SUM_IN_TOC) Var(rs6000_misc_flags) +Place/do not place symbol+offset constants in TOC ; Output only one TOC entry per module. Normally linking fails if ; there are more than 16K unique variables/constants in an executable. With @@ -285,7 +310,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -293,7 +318,7 @@ Target Report Put everything in the regular TOC mvrsave -Target Report Var(TARGET_ALTIVEC_VRSAVE) Save +Target Report Mask(ALTIVEC_VRSAVE) Var(rs6000_misc_flags) Generate VRSAVE instructions when generating AltiVec code mvrsave=no @@ -309,7 +334,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no @@ -321,13 +346,9 @@ Target RejectNegative Alias(misel) Deprecated option. Use -misel instead mspe -Target Var(rs6000_spe) Save +Target Report Mask(SPE) Var(rs6000_isa_flags) Generate SPE SIMD instructions on E500 -mpaired -Target Var(rs6000_paired_float) Save -Generate PPC750CL paired-single instructions - mspe=no Target RejectNegative Alias(mspe) NegativeAlias Deprecated option. Use -mno-spe instead @@ -336,9 +357,54 @@ mspe=yes Target RejectNegative Alias(mspe) Deprecated option. Use -mspe instead -mdebug= -Target RejectNegative Joined --mdebug= Enable debug output +mpaired +Target Report Mask(PAIRED_FLOAT) Var(rs6000_isa_flags) +Generate PPC750CL paired-single instructions + +mdebug=all +Target Report RejectNegative Undocumented Mask(DEBUG_ALL) Var(rs6000_debug_flags) + +mdebug=addr +Target Report RejectNegative Undocumented Mask(DEBUG_ADDR) Var(rs6000_debug_flags) + +mdebug=noaddr +Target Report RejectNegative Undocumented InverseMask(DEBUG_ADDR) Var(rs6000_debug_flags) + +mdebug=arg +Target Report RejectNegative Undocumented Mask(DEBUG_ARG) Var(rs6000_debug_flags) + +mdebug=noarg +Target Report RejectNegative Undocumented InverseMask(DEBUG_ARG) Var(rs6000_debug_flags) + +mdebug=builtin +Target Report RejectNegative Undocumented Mask(DEBUG_BUILTIN) Var(rs6000_debug_flags) + +mdebug=nobuiltin +Target Report RejectNegative Undocumented InverseMask(DEBUG_BUILTIN) Var(rs6000_debug_flags) + +mdebug=cost +Target Report RejectNegative Undocumented Mask(DEBUG_COST) Var(rs6000_debug_flags) + +mdebug=nocost +Target Report RejectNegative Undocumented InverseMask(DEBUG_COST) Var(rs6000_debug_flags) + +mdebug=reg +Target Report RejectNegative Undocumented Mask(DEBUG_REG) Var(rs6000_debug_flags) + +mdebug=noreg +Target Report RejectNegative Undocumented InverseMask(DEBUG_REG) Var(rs6000_debug_flags) + +mdebug=stack +Target Report RejectNegative Undocumented Mask(DEBUG_STACK) Var(rs6000_debug_flags) + +mdebug=nostack +Target Report RejectNegative Undocumented InverseMask(DEBUG_STACK) Var(rs6000_debug_flags) + +mdebug=target +Target Report RejectNegative Undocumented Mask(DEBUG_TARGET) Var(rs6000_debug_flags) + +mdebug=notarget +Target Report RejectNegative Undocumented InverseMask(DEBUG_TARGET) Var(rs6000_debug_flags) mabi=altivec Target RejectNegative Var(rs6000_altivec_abi) Save @@ -397,19 +463,19 @@ EnumValue Enum(rs6000_traceback_type) String(no) Value(traceback_none) mlongcall -Target Report Var(rs6000_default_long_calls) Save +Target Report Mask(LONG_CALLS) Var(rs6000_isa_flags) Avoid all range limits on call instructions mgen-cell-microcode -Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save +Target Report Mask(GEN_CELL_MICROCODE) Var(rs6000_misc_flags) Generate Cell microcode mwarn-cell-microcode -Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save +Target Report Warning Mask(WARN_CELL_MICROCODE) Var(rs6000_misc_flags) Warn when a Cell microcoded instruction is emitted mwarn-altivec-long -Target Var(rs6000_warn_altivec_long) Init(1) Save +Target Report Mask(WARN_ALTIVEC_LONG) Var(rs6000_misc_flags) Warn about deprecated 'vector long ...' AltiVec type usage mfloat-gprs= @@ -497,13 +563,13 @@ EnumValue Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) mxilinx-fpu -Target Var(rs6000_xilinx_fpu) Save +Target Report Var(rs6000_isa_flags) Mask(XILINX_FPU) Specify Xilinx FPU. mpointers-to-nested-functions -Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save +Target Report Mask(POINTERS_TO_NESTED_FUNCTIONS) Var(rs6000_misc_flags) Use/do not use r11 to hold the static link in calls to functions via pointers. msave-toc-indirect -Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save +Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_misc_flags) Control whether we save the TOC in the prologue for indirect calls or generate the save inline Index: gcc/config/rs6000/linuxaltivec.h =================================================================== --- gcc/config/rs6000/linuxaltivec.h (revision 191266) +++ gcc/config/rs6000/linuxaltivec.h (working copy) @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ALTIVEC +#define TARGET_DEFAULT OPTION_MASK_ALTIVEC #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 191266) +++ gcc/config/rs6000/linux64.h (working copy) @@ -37,7 +37,7 @@ #else -#define DEFAULT_ARCH64_P (TARGET_DEFAULT & MASK_64BIT) +#define DEFAULT_ARCH64_P (TARGET_DEFAULT & OPTION_MASK_64BIT) #define RS6000_BI_ARCH_P 1 #endif @@ -61,7 +61,7 @@ extern int dot_symbols; #define DOT_SYMBOLS dot_symbols #endif -#define TARGET_PROFILE_KERNEL profile_kernel +#define TARGET_PROFILE_KERNEL OPTION_PROFILE_KERNEL #define TARGET_USES_LINUX64_OPT 1 #ifdef HAVE_LD_LARGE_TOC @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,27 +103,28 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ { \ - target_prototype = 0; \ + rs6000_misc_flags &= ~OPTION_MASK_PROTOTYPE; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -136,8 +137,8 @@ extern int dot_symbols; SET_CMODEL (CMODEL_MEDIUM); \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC \ + | OPTION_MASK_NO_SUM_IN_TOC); \ } \ } \ } \ @@ -147,7 +148,7 @@ extern int dot_symbols; error (INVALID_32BIT, "32"); \ if (TARGET_PROFILE_KERNEL) \ { \ - TARGET_PROFILE_KERNEL = 0; \ + rs6000_misc_flags &= ~OPTION_MASK_PROFILE_KERNEL; \ error (INVALID_32BIT, "profile-kernel"); \ } \ if (global_options_set.x_rs6000_current_cmodel) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/darwin.h =================================================================== --- gcc/config/rs6000/darwin.h (revision 191266) +++ gcc/config/rs6000/darwin.h (working copy) @@ -280,7 +280,7 @@ extern int darwin_emit_branch_islands; default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 191266) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -213,7 +213,7 @@ static GTY(()) section *toc_section; struct builtin_description { - const unsigned int mask; + const HOST_WIDE_INT mask; const enum insn_code icode; const char *const name; const enum rs6000_builtins code; @@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); /* Target cpu costs. */ @@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = { struct rs6000_builtin_info_type { const char *name; const enum insn_code icode; - const unsigned mask; + const HOST_WIDE_INT mask; const unsigned attr; }; @@ -1015,6 +1015,9 @@ bool (*rs6000_cannot_change_mode_class_p const int INSN_NOT_AVAILABLE = -1; +static void rs6000_print_isa_options (FILE *, HOST_WIDE_INT); +static void rs6000_print_misc_options (FILE *, HOST_WIDE_INT); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct @@ -1115,8 +1118,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; -#ifndef MASK_STRICT_ALIGN -#define MASK_STRICT_ALIGN 0 +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL #define TARGET_PROFILE_KERNEL 0 @@ -1458,53 +1461,12 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ const enum processor_type processor; /* Processor type enum value. */ - const int target_enable; /* Target flags to enable. */ + const HOST_WIDE_INT target_enable; /* Target flags to enable. */ }; static struct rs6000_ptt const processor_target_table[] = @@ -1715,9 +1677,12 @@ rs6000_debug_reg_print (int first_regno, } } -#define DEBUG_FMT_D "%-32s= %d\n" -#define DEBUG_FMT_X "%-32s= 0x%x\n" -#define DEBUG_FMT_S "%-32s= %s\n" +#define DEBUG_FMT_ID "%-32s= " +#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" +#define DEBUG_FMT_X DEBUG_FMT_ID "%#x\n" +#define DEBUG_FMT_WX DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX ": " +#define DEBUG_FMT_WX2 DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX "\n" +#define DEBUG_FMT_S DEBUG_FMT_ID "%s\n" /* Print various interesting information with -mdebug=reg. */ static void @@ -1728,11 +1693,13 @@ rs6000_debug_reg_global (void) int m; char costly_num[20]; char nop_num[20]; + char flags_buffer[40]; const char *costly_str; const char *nop_str; const char *trace_str; const char *abi_str; const char *cmodel_str; + struct cl_target_option cl_opts; /* Map enum rs6000_vector to string. */ static const char *rs6000_debug_vector_unit[] = { @@ -1812,12 +1779,90 @@ rs6000_debug_reg_global (void) } if (rs6000_cpu_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "cpu", - processor_target_table[rs6000_cpu_index].name); + { + const char *name = processor_target_table[rs6000_cpu_index].name; + fprintf (stderr, DEBUG_FMT_S, "cpu", name); + sprintf (flags_buffer, "%s cpu flags", name); + + if (processor_target_table[rs6000_cpu_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_cpu_index].target_enable; + fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags); + rs6000_print_isa_options (stderr, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, ""); + } + else + fprintf (stderr, DEBUG_FMT_S, "cpu", ""); if (rs6000_tune_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "tune", - processor_target_table[rs6000_tune_index].name); + { + const char *name = processor_target_table[rs6000_tune_index].name; + fprintf (stderr, DEBUG_FMT_S, "tune", name); + sprintf (flags_buffer, "%s tune flags", name); + + if (processor_target_table[rs6000_tune_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_tune_index].target_enable; + fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags); + rs6000_print_isa_options (stderr, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, ""); + } + else + fprintf (stderr, DEBUG_FMT_S, "tune", ""); + + cl_target_option_save (&cl_opts, &global_options); + if (rs6000_isa_flags) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags", rs6000_isa_flags); + rs6000_print_isa_options (stderr, rs6000_isa_flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags", ""); + + if (rs6000_isa_flags_explicit) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); + rs6000_print_isa_options (stderr, rs6000_isa_flags_explicit); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags_explicit", ""); + + if (rs6000_misc_flags) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_misc_flags", rs6000_misc_flags); + rs6000_print_misc_options (stderr, rs6000_misc_flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_misc_flags", ""); + + if (rs6000_misc_flags_explicit) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_misc_flags_explicit", + rs6000_misc_flags_explicit); + rs6000_print_misc_options (stderr, rs6000_misc_flags_explicit); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_misc_flags_explicit", ""); + + fprintf (stderr, DEBUG_FMT_WX2, "rs6000_debug_flags", rs6000_debug_flags); + fprintf (stderr, DEBUG_FMT_WX2, "rs6000_debug_flags_explicit", + rs6000_debug_flags_explicit); + + if (rs6000_builtin_mask) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_builtin_mask", + rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_builtin_mask", ""); switch (rs6000_sched_costly_dep) { @@ -1935,7 +1980,15 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + + fprintf (stderr, DEBUG_FMT_S, "plt-format", + TARGET_SECURE_PLT ? "secure" : "bss"); + fprintf (stderr, DEBUG_FMT_S, "struct-return", + aix_struct_return ? "aix" : "sysv"); fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]); + fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]); fprintf (stderr, DEBUG_FMT_S, "align_branch", tf[!!rs6000_align_branch_targets]); fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size); @@ -1947,7 +2000,6 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); - fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask); } /* Initialize the various global tables that are based on register size. */ @@ -2302,7 +2354,7 @@ darwin_rs6000_override_options (void) /* The Darwin ABI always includes AltiVec, can't be (validly) turned off. */ rs6000_altivec_abi = 1; - TARGET_ALTIVEC_VRSAVE = 1; + rs6000_misc_flags |= OPTION_MASK_ALTIVEC_VRSAVE; rs6000_current_abi = ABI_DARWIN; if (DEFAULT_ABI == ABI_DARWIN @@ -2311,21 +2363,18 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) - { - rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; - } + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT | OPTION_MASK_LONG_CALLS; /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2333,10 +2382,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2348,26 +2397,25 @@ darwin_rs6000_override_options (void) #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 #endif -/* Return the builtin mask of the various options used that could affect which - builtins were used. In the past we used target_flags, but we've run out of - bits, and some options like SPE and PAIRED are no longer in - target_flags. */ - -unsigned -rs6000_builtin_mask_calculate (void) -{ - return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) - | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) - | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) - | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) - | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) - | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) - | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) - | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) - | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); +/* Helper function for rs6000_option_override_internal, that returns whether an + option is set in the tuning flags, but allow an override from the switches + if it was set explicitly. */ +static inline HOST_WIDE_INT +rs6000_operand_tuning_flag (HOST_WIDE_INT option_mask) +{ + HOST_WIDE_INT mask = rs6000_isa_flags; + + if (rs6000_tune_index >= 0 && + (rs6000_isa_flags_explicit & option_mask) == 0) + mask = processor_target_table[rs6000_tune_index].target_enable; + + return (mask & option_mask); } + /* Allow the explicit debug switches to override the tuning settings. If no + explicit switch, fall back to the tuning options instead of the cpu + options. */ + /* Override command line options. Mostly we process the processor type and sometimes adjust other TARGET_ options. */ @@ -2380,13 +2428,17 @@ rs6000_option_override_internal (bool gl /* The default cpu requested at configure time, if any. */ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; - int set_masks; + HOST_WIDE_INT set_masks; int cpu_index; int tune_index; struct cl_target_option *main_target_opt = ((global_init_p || target_option_default_node == NULL) ? NULL : TREE_TARGET_OPTION (target_option_default_node)); + /* If -mdebug=all, enable all debug options excepct those explicitly set. */ + if (TARGET_DEBUG_ALL) + rs6000_debug_flags |= (ALL_DEBUG_MASKS & ~rs6000_debug_flags_explicit); + /* On 64-bit Darwin, power alignment is ABI-incompatible with some C library functions, so warn about it. The flag may be useful for performance studies from time to time though, so don't disable it @@ -2417,18 +2469,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu= and -mtune= argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2457,9 +2515,9 @@ rs6000_option_override_internal (bool gl gcc_assert (cpu_index >= 0); - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2485,37 +2543,25 @@ rs6000_option_override_internal (bool gl /* Pick defaults for SPE related control flags. Do this early to make sure that the TARGET_ macros are representative ASAP. */ - { - int spe_capable_cpu = - (rs6000_cpu == PROCESSOR_PPC8540 - || rs6000_cpu == PROCESSOR_PPC8548); - - if (!global_options_set.x_rs6000_spe_abi) - rs6000_spe_abi = spe_capable_cpu; - - if (!global_options_set.x_rs6000_spe) - rs6000_spe = spe_capable_cpu; - - if (!global_options_set.x_rs6000_float_gprs) - rs6000_float_gprs = - (rs6000_cpu == PROCESSOR_PPC8540 ? 1 - : rs6000_cpu == PROCESSOR_PPC8548 ? 2 - : 0); - } + if (rs6000_cpu == PROCESSOR_PPC8540 || rs6000_cpu == PROCESSOR_PPC8548) + { + if (!global_options_set.x_rs6000_spe_abi) + rs6000_spe_abi = 1; + + if ((rs6000_isa_flags_explicit & OPTION_MASK_SPE) == 0) + rs6000_isa_flags |= OPTION_MASK_SPE; + + if (!global_options_set.x_rs6000_float_gprs) + rs6000_float_gprs = (rs6000_cpu == PROCESSOR_PPC8540) ? 1 : 2; + } + else if (!global_options_set.x_rs6000_spe_abi) + rs6000_spe_abi = 0; - if (global_options_set.x_rs6000_spe_abi - && rs6000_spe_abi - && !TARGET_SPE_ABI) - error ("not configured for SPE ABI"); - - if (global_options_set.x_rs6000_spe - && rs6000_spe - && !TARGET_SPE) - error ("not configured for SPE instruction set"); if (main_target_opt != NULL && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi) - || (main_target_opt->x_rs6000_spe != rs6000_spe) + || (((main_target_opt->x_rs6000_isa_flags ^ rs6000_isa_flags) + & OPTION_MASK_SPE) != 0) || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs))) error ("target attribute or pragma changes SPE ABI"); @@ -2536,15 +2582,16 @@ rs6000_option_override_internal (bool gl /* Disable Cell microcode if we are optimizing for the Cell and not optimizing for size. */ - if (rs6000_gen_cell_microcode == -1) - rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL - && !optimize_size); + if ((rs6000_misc_flags_explicit & OPTION_MASK_GEN_CELL_MICROCODE) == 0 + && !(rs6000_cpu == PROCESSOR_CELL && !optimize_size)) + rs6000_misc_flags |= OPTION_MASK_GEN_CELL_MICROCODE; /* If we are optimizing big endian systems for space and it's OK to use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ - if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + if (BYTES_BIG_ENDIAN && optimize_size && TARGET_GEN_CELL_MICROCODE) + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2556,15 +2603,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2576,10 +2623,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2588,11 +2635,12 @@ rs6000_option_override_internal (bool gl systems at this point. */ else if (!BYTES_BIG_ENDIAN) msg = N_("-mvsx used with little endian code"); - else if (TARGET_AVOID_XFORM > 0) + else if (TARGET_AVOID_XFORM) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2601,27 +2649,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-