From patchwork Sun Sep 16 23:08:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 184178 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 195B92C008E for ; Mon, 17 Sep 2012 09:09:39 +1000 (EST) Received: from localhost ([::1]:34668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDNy5-0007nE-0f for incoming@patchwork.ozlabs.org; Sun, 16 Sep 2012 19:09:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDNxK-0005yK-MI for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:08:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDNxJ-0006yS-CB for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:08:50 -0400 Received: from hall.aurel32.net ([88.191.126.93]:60373) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDNxJ-0006x8-5f for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:08:49 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TDNx9-0006Fc-9x; Mon, 17 Sep 2012 01:08:39 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TDNx9-0003j4-8K; Mon, 17 Sep 2012 01:08:39 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2012 01:08:34 +0200 Message-Id: <1347836915-14091-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1347836915-14091-1-git-send-email-aurelien@aurel32.net> References: <1347836915-14091-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Peter Maydell , Aurelien Jarno Subject: [Qemu-devel] [PATCH 4/5] target-arm: optimize helper_sar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org helper_sar doesn't need env. It can also be marked const and pure. Signed-off-by: Aurelien Jarno --- target-arm/helper.h | 2 +- target-arm/op_helper.c | 2 +- target-arm/translate.c | 6 ++++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index b123d3e..b2d2670 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -145,7 +145,7 @@ DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) DEF_HELPER_3(adc_cc, i32, env, i32, i32) DEF_HELPER_3(sbc_cc, i32, env, i32, i32) -DEF_HELPER_3(sar, i32, env, i32, i32) +DEF_HELPER_FLAGS_2(sar, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32) DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 5fcd12c..0148818 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -355,7 +355,7 @@ uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b) /* Similarly for variable shift instructions. */ -uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i) +uint32_t HELPER(sar)(uint32_t x, uint32_t i) { int shift = i & 0xff; if (shift >= 32) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9c29065..cb5bca4 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -542,7 +542,9 @@ static inline void gen_arm_shift_reg(TCGv var, int shiftop, case 1: gen_shr(var, var, shift); break; - case 2: gen_helper_sar(var, cpu_env, var, shift); break; + case 2: + gen_helper_sar(var, var, shift); + break; case 3: tcg_gen_andi_i32(shift, shift, 0x1f); tcg_gen_rotr_i32(var, var, shift); break; } @@ -9201,7 +9203,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) break; case 0x4: /* asr */ if (s->condexec_mask) { - gen_helper_sar(tmp2, cpu_env, tmp2, tmp); + gen_helper_sar(tmp2, tmp2, tmp); } else { gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); gen_logic_CC(tmp2);