Patchwork [4/5] target-arm: optimize helper_sar

login
register
mail settings
Submitter Aurelien Jarno
Date Sept. 16, 2012, 11:08 p.m.
Message ID <1347836915-14091-5-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/184178/
State New
Headers show

Comments

Aurelien Jarno - Sept. 16, 2012, 11:08 p.m.
helper_sar doesn't need env. It can also be marked const and pure.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-arm/helper.h    |    2 +-
 target-arm/op_helper.c |    2 +-
 target-arm/translate.c |    6 ++++--
 3 files changed, 6 insertions(+), 4 deletions(-)

Patch

diff --git a/target-arm/helper.h b/target-arm/helper.h
index b123d3e..b2d2670 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -145,7 +145,7 @@  DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
 DEF_HELPER_3(adc_cc, i32, env, i32, i32)
 DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
 
-DEF_HELPER_3(sar, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(sar, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
 DEF_HELPER_3(shl_cc, i32, env, i32, i32)
 DEF_HELPER_3(shr_cc, i32, env, i32, i32)
 DEF_HELPER_3(sar_cc, i32, env, i32, i32)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 5fcd12c..0148818 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -355,7 +355,7 @@  uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
 
 /* Similarly for variable shift instructions.  */
 
-uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
+uint32_t HELPER(sar)(uint32_t x, uint32_t i)
 {
     int shift = i & 0xff;
     if (shift >= 32)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9c29065..cb5bca4 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -542,7 +542,9 @@  static inline void gen_arm_shift_reg(TCGv var, int shiftop,
         case 1:
             gen_shr(var, var, shift);
             break;
-        case 2: gen_helper_sar(var, cpu_env, var, shift); break;
+        case 2:
+            gen_helper_sar(var, var, shift);
+            break;
         case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
                 tcg_gen_rotr_i32(var, var, shift); break;
         }
@@ -9201,7 +9203,7 @@  static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
             break;
         case 0x4: /* asr */
             if (s->condexec_mask) {
-                gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
+                gen_helper_sar(tmp2, tmp2, tmp);
             } else {
                 gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
                 gen_logic_CC(tmp2);