From patchwork Thu Sep 13 17:37:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Weil X-Patchwork-Id: 183688 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 84A532C0089 for ; Fri, 14 Sep 2012 03:38:26 +1000 (EST) Received: from localhost ([::1]:45659 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCDMu-0007fQ-Ij for incoming@patchwork.ozlabs.org; Thu, 13 Sep 2012 13:38:24 -0400 Received: from eggs.gnu.org ([208.118.235.92]:60001) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCDMV-00075v-Ta for qemu-devel@nongnu.org; Thu, 13 Sep 2012 13:38:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TCDMN-0008QV-Rj for qemu-devel@nongnu.org; Thu, 13 Sep 2012 13:37:59 -0400 Received: from v220110690675601.yourvserver.net ([78.47.199.172]:36216) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCDMN-0008QC-Lh for qemu-devel@nongnu.org; Thu, 13 Sep 2012 13:37:51 -0400 Received: from localhost (v220110690675601.yourvserver.net.local [127.0.0.1]) by v220110690675601.yourvserver.net (Postfix) with ESMTP id 1039D728001E; Thu, 13 Sep 2012 19:37:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at weilnetz.de Received: from v220110690675601.yourvserver.net ([127.0.0.1]) by localhost (v220110690675601.yourvserver.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vRZXxulsI5+I; Thu, 13 Sep 2012 19:37:50 +0200 (CEST) Received: by v220110690675601.yourvserver.net (Postfix, from userid 1000) id 866C87280033; Thu, 13 Sep 2012 19:37:50 +0200 (CEST) From: Stefan Weil To: Blue Swirl Date: Thu, 13 Sep 2012 19:37:43 +0200 Message-Id: <1347557866-7256-2-git-send-email-sw@weilnetz.de> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1347557866-7256-1-git-send-email-sw@weilnetz.de> References: <1347557866-7256-1-git-send-email-sw@weilnetz.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 78.47.199.172 Cc: Peter Maydell , Stefan Weil , Alexander Graf , qemu-devel@nongnu.org, Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 1/4] w64: Fix TCG helper functions with 5 arguments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org TCG uses 6 registers for function arguments on 64 bit Linux hosts, but only 4 registers on W64 hosts. Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number of arguments for some important helper functions from 4 to 5 which triggered a bug for W64 hosts: QEMU aborts when executing helper_lcall_real in the guest's BIOS because function tcg_target_get_call_iarg_regs_count always returned 6. As W64 has only 4 registers for arguments, the 5th argument must be passed on the stack using a correct stack offset. Signed-off-by: Stefan Weil Reviewed-by: Aurelien Jarno --- tcg/i386/tcg-target.c | 2 +- tcg/i386/tcg-target.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index da17bba..43b5572 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -118,7 +118,7 @@ static void patch_reloc(uint8_t *code_ptr, int type, static inline int tcg_target_get_call_iarg_regs_count(int flags) { if (TCG_TARGET_REG_BITS == 64) { - return 6; + return ARRAY_SIZE(tcg_target_call_iarg_regs); } return 0; diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index c3cfe05..87417d0 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -67,7 +67,11 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_ESP #define TCG_TARGET_STACK_ALIGN 16 +#if defined(_WIN64) +#define TCG_TARGET_CALL_STACK_OFFSET 32 +#else #define TCG_TARGET_CALL_STACK_OFFSET 0 +#endif /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1