m68k: implmenent more ColdFire 5208 interrupt controller functionality

Submitted by Greg Ungerer on Sept. 13, 2012, 6:31 a.m.

Details

Message ID 1347517917-16644-1-git-send-email-gerg@snapgear.com
State New
Headers show

Commit Message

Greg Ungerer Sept. 13, 2012, 6:31 a.m.
From: Greg Ungerer <gerg@uclinux.org>

Implement the SIMR and CIMR registers of the 5208 interrupt controller.
These are used by modern versions of Linux running on ColdFire (not sure
of the exact version they were introduced, but they have been in for quite
a while now).

Without this change when attempting to run a linux-3.5 kernel you will
see:

  qemu: hardware error: mcf_intc_write: Bad write offset 28

and execution will stop and dump out.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 hw/mcf_intc.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

Patch hide | download patch | download mbox

diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index cc1a5f3..1811d0d 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -102,6 +102,20 @@  static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
     case 0x0c:
         s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
         break;
+    case 0x1c:
+        if (val & 0x40) {
+            s->imr = 0xffffffffffffffffull;
+        } else {
+            s->imr |= (0x1ull << (val & 0x3f));
+        }
+        break;
+    case 0x1d:
+        if (val & 0x40) {
+            s->imr = 0ull;
+        } else {
+            s->imr &= ~(0x1ull << (val & 0x3f));
+        }
+        break;
     default:
         hw_error("mcf_intc_write: Bad write offset %d\n", offset);
         break;