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[i386] Enable prefetchw in processor alias table for AMD targets

Message ID 20120911090321.28497.41562.sendpatchset@adcape-a.amd.com
State New
Headers show

Commit Message

Kumar, Venkataramanan Sept. 11, 2012, 9:03 a.m. UTC 
Hi Maintainers,

This patch enables "prefetchw" ISA in the processor alias table for targets amdfam10,barcelona and bdver1,2 and btver1,2.

GCC regression test passes with the patch.

Ok for trunk?

Change log:

2012-09-11  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>

    * config/i386/i386.c (processor_alias_table): Enable PTA_PRFCHW
    for targets amdfam10, barcelona, bdver1, bdver2, btver1 and btver2.

Comments

Uros Bizjak Sept. 12, 2012, 3:43 p.m. UTC | #1 
On Tue, Sep 11, 2012 at 11:03 AM,  <venkataramanan.kumar@amd.com> wrote:
> Hi Maintainers,
>
> This patch enables "prefetchw" ISA in the processor alias table for targets amdfam10,barcelona and bdver1,2 and btver1,2.
>
> GCC regression test passes with the patch.
>
> Ok for trunk?
>
> Change log:
>
> 2012-09-11  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
>
>     * config/i386/i386.c (processor_alias_table): Enable PTA_PRFCHW
>     for targets amdfam10, barcelona, bdver1, bdver2, btver1 and btver2.

Please note that amdfam10 and barcelona are already generating
prefetchw due to PTA_3DNOW flag, so these targets can be removed from
the patch.

The patch is OK for mainline with that change. Please commit the patch.

Thanks,
Uros.
diff mbox

Patch

Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c	(revision 190345)
+++ gcc/config/i386/i386.c	(working copy)
@@ -3151,31 +3151,33 @@ 
 	| PTA_SSE2 | PTA_NO_SAHF},
       {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
 	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
+	| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM 
+	| PTA_PRFCHW},
       {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
 	PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
-	| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
+	| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM
+	| PTA_PRFCHW},
       {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
 	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
-	| PTA_XOP | PTA_LWP},
+	| PTA_XOP | PTA_LWP | PTA_PRFCHW},
       {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
 	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
 	| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
-	| PTA_FMA},
+	| PTA_FMA | PTA_PRFCHW},
       {"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,
         PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
-        | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16},
+        | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW},
       {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
 	PTA_HLE /* flags are only used for -march switch.  */ },
       {"btver2", PROCESSOR_BTVER2, CPU_GENERIC64,
 	PTA_64BIT | PTA_MMX |  PTA_SSE  | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
 	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
-	| PTA_BMI | PTA_F16C | PTA_MOVBE},
+	| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW},
       {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
 	PTA_64BIT
         | PTA_HLE /* flags are only used for -march switch.  */ },