From patchwork Mon Sep 10 15:28:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 182911 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 79A0F2C00D5 for ; Tue, 11 Sep 2012 01:28:54 +1000 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1347895734; h=Comment: DomainKey-Signature:Received:Received:Received:Received:Received: Message-ID:Date:From:User-Agent:MIME-Version:To:Subject: Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:Sender:Delivered-To; bh=yyd5oPy kjRgGPC5bc7Ski+VQPng=; b=yKsqo0PWDGJclsDo5YK07Xpc9SF5UXTSiE160zr KRkof/TZC2/rZWutkFv3oZHjfI42JYHOofIPirCEDaTkSjuiqGevi4np2LtCDhMG wBQnh+bLOFRw8zLCnppatSHovu59dFQL4wGpTXzwWRXwqRXBV1qh2meysdK2+O63 EppU= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Message-ID:Date:From:User-Agent:MIME-Version:To:Subject:X-MC-Unique:Content-Type:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=IYDYsLAW4mIrb9NWEPsSsyPuRwZI8FWoDJkeg/DuMjpbhrtU52uAXjYum9s3Sw MvRsM57WGSUtU2PAgXhHhFC/Q3+5UqGnvRripHzJZxzIzznFjyIDOquX0XuU0c6G S0hLpgYlcWw9tOUbY3FnvCKu8rTaRZd9hdzgotyHbqx2Q=; Received: (qmail 13808 invoked by alias); 10 Sep 2012 15:28:49 -0000 Received: (qmail 13799 invoked by uid 22791); 10 Sep 2012 15:28:48 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Sep 2012 15:28:36 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 10 Sep 2012 16:28:33 +0100 Received: from [10.1.79.66] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 10 Sep 2012 16:28:31 +0100 Message-ID: <504E071F.3020208@arm.com> Date: Mon, 10 Sep 2012 16:28:31 +0100 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch][AArch64] Implement TARGET_SHIFT_TRUNCATION_MASK. X-MC-Unique: 112091016283315501 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, The attached patch implements TARGET_SHIFT_TRUNCATION_MASK target hook. Regression-tested on aarch64-none-elf. OK for aarch64-branch? Thanks, Tejas Belagod ARM. PS: This patch applies over vldn-vstn.txt sent earlier. Changelog: 2012-09-10 Tejas Belagod gcc/ * config/aarch64/aarch64.c (aarch64_shift_truncation_mask): Define. (TARGET_SHIFT_TRUNCATION_MASK): Define. * config/aarch64/aarch64.h (SHIFT_COUNT_TRUNCATED): Conditionalize on TARGET_SIMD. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 20b23d2..7952530 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6677,6 +6677,14 @@ aarch64_simd_attr_length_move (rtx insn) return 4; } +static unsigned HOST_WIDE_INT +aarch64_shift_truncation_mask (enum machine_mode mode) +{ + return + (aarch64_vector_mode_supported_p (mode) + || aarch64_vect_struct_mode_p (mode)) ? 0 : (GET_MODE_BITSIZE (mode) - 1); +} + #ifndef TLS_SECTION_ASM_FLAG #define TLS_SECTION_ASM_FLAG 'T' #endif @@ -6930,6 +6938,9 @@ aarch64_c_mode_for_suffix (char suffix) #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload +#undef TARGET_SHIFT_TRUNCATION_MASK +#define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask + #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 28cafa9..8dfcd44 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -786,7 +786,7 @@ enum aarch64_builtins : 0) -#define SHIFT_COUNT_TRUNCATED 1 +#define SHIFT_COUNT_TRUNCATED !TARGET_SIMD /* Callee only saves lower 64-bits of a 128-bit register. Tell the compiler the callee clobbers the top 64-bits when restoring the