Patchwork [AArch64] Implement TARGET_SHIFT_TRUNCATION_MASK.

login
register
mail settings
Submitter Tejas Belagod
Date Sept. 10, 2012, 3:28 p.m.
Message ID <504E071F.3020208@arm.com>
Download mbox | patch
Permalink /patch/182911/
State New
Headers show

Comments

Tejas Belagod - Sept. 10, 2012, 3:28 p.m.
Hi,

The attached patch implements TARGET_SHIFT_TRUNCATION_MASK target hook.

Regression-tested on aarch64-none-elf. OK for aarch64-branch?

Thanks,
Tejas Belagod
ARM.

PS: This patch applies over vldn-vstn.txt sent earlier.

Changelog:

2012-09-10  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_shift_truncation_mask): Define.
	(TARGET_SHIFT_TRUNCATION_MASK): Define.
	* config/aarch64/aarch64.h (SHIFT_COUNT_TRUNCATED): Conditionalize on
	TARGET_SIMD.
Marcus Shawcroft - Sept. 25, 2012, 6:16 p.m.
On 10/09/12 16:28, Tejas Belagod wrote:
> gcc/
> 	* config/aarch64/aarch64.c (aarch64_shift_truncation_mask): Define.
> 	(TARGET_SHIFT_TRUNCATION_MASK): Define.
> 	* config/aarch64/aarch64.h (SHIFT_COUNT_TRUNCATED): Conditionalize on
> 	TARGET_SIMD.

Committed to aarch64-branch and aarch64-4.7-branch.
/Marcus

Patch

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 20b23d2..7952530 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6677,6 +6677,14 @@  aarch64_simd_attr_length_move (rtx insn)
   return 4;
 }
 
+static unsigned HOST_WIDE_INT
+aarch64_shift_truncation_mask (enum machine_mode mode)
+{
+  return
+    (aarch64_vector_mode_supported_p (mode)
+     || aarch64_vect_struct_mode_p (mode)) ? 0 : (GET_MODE_BITSIZE (mode) - 1);
+}
+
 #ifndef TLS_SECTION_ASM_FLAG
 #define TLS_SECTION_ASM_FLAG 'T'
 #endif
@@ -6930,6 +6938,9 @@  aarch64_c_mode_for_suffix (char suffix)
 #undef TARGET_SECONDARY_RELOAD
 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
 
+#undef TARGET_SHIFT_TRUNCATION_MASK
+#define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
+
 #undef TARGET_SETUP_INCOMING_VARARGS
 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
 
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 28cafa9..8dfcd44 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -786,7 +786,7 @@  enum aarch64_builtins
    : 0)
 
 
-#define SHIFT_COUNT_TRUNCATED 1
+#define SHIFT_COUNT_TRUNCATED !TARGET_SIMD
 
 /* Callee only saves lower 64-bits of a 128-bit register.  Tell the
    compiler the callee clobbers the top 64-bits when restoring the