From patchwork Mon Sep 10 15:11:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 182906 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D6DA72C0088 for ; Tue, 11 Sep 2012 01:11:56 +1000 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1347894717; h=Comment: DomainKey-Signature:Received:Received:Received:Received:Received: Message-ID:Date:From:User-Agent:MIME-Version:To:Subject: Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:Sender:Delivered-To; bh=VCjnuba LbpFrDgFHs9pfRS7uKDY=; b=j+keWmv/yvzjc2ln4de0V8p+g7dC9hNnQgKSzPt tIhn7QqdR7Y5Iw2Q5skeV+UuCgeP3hCa4kpYnqCzzaiCGFyfAAWYGcByI1njJnA3 QypDMCOEnvFM9MDmf2IVkKMZv01HBvUFFHFagVTlVJxM7vXOddZe8tlzBPhIa0Nb RsNs= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Message-ID:Date:From:User-Agent:MIME-Version:To:Subject:X-MC-Unique:Content-Type:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=v+CByULOYKitIr78y2drwtgjsZaxsqv7dW1sjJFn5Rc8CB/IEB+Y8nOY6ajmoZ pjAY5eLHsup36FB9/PIGs2BJ0gfrZJLXQ4+chCm74UXGTWlGYpta8SAy3PTowNTG nQ5poh9VLDBgQVdsBPXiuSvbTo6hE9XdhVMcMsG270gck=; Received: (qmail 29805 invoked by alias); 10 Sep 2012 15:11:50 -0000 Received: (qmail 29783 invoked by uid 22791); 10 Sep 2012 15:11:47 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Sep 2012 15:11:34 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 10 Sep 2012 16:11:33 +0100 Received: from [10.1.79.66] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 10 Sep 2012 16:11:32 +0100 Message-ID: <504E0323.6020100@arm.com> Date: Mon, 10 Sep 2012 16:11:31 +0100 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch][AArch64] Tighten predicate for CMP pattern. X-MC-Unique: 112091016113305201 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch tightens the predicate for the CMP pattern. It makes it restrictive to accept reg or zero as prescribed by the architecture. Regression-tested on aarch64-none-elf. OK for aarch64-branch? Thanks, Tejas Belagod ARM. PS: This patch applies over vldn-vstn.txt sent out earlier. Changelog: 2012-09-10 Tejas Belagod gcc/ * config/aarch64/aarch64-simd.md (aarch64_cm): Tighten predicate for operand 2 of the compare pattern to accept register or zero. * config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index d3f8ef2..50114aa 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2670,7 +2670,7 @@ [(set (match_operand: 0 "register_operand" "=w,w") (unspec: [(match_operand:VSDQ_I_DI 1 "register_operand" "w,w") - (match_operand:VSDQ_I_DI 2 "nonmemory_operand" "w,Z")] + (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")] VCMP_S))] "TARGET_SIMD" "@ diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 328e5cf..f40ab56 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -265,3 +265,10 @@ { return aarch64_simd_shift_imm_p (op, mode, false); }) + +(define_predicate "aarch64_simd_reg_or_zero" + (and (match_code "reg,subreg,const_int,const_vector") + (ior (match_operand 0 "register_operand") + (ior (match_test "op == const0_rtx") + (match_test "aarch64_simd_imm_zero_p (op, mode)"))))) +