Patchwork [AArch64] Split a move of Q-reg vectors contained in general regs.

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Submitter Tejas Belagod
Date Sept. 10, 2012, 3:05 p.m.
Message ID <504E01D6.5090809@arm.com>
Download mbox | patch
Permalink /patch/182905/
State New
Headers show

Comments

Tejas Belagod - Sept. 10, 2012, 3:05 p.m.
Hi,

This patch fixes the mov pattern to split a move between general regs that
contain a Q-reg vector value.

Regression-tested on aarch64-none-elf. OK for aarch64-branch?

Thanks,
Tejas Belagod
ARM.

Changelog:

2012-09-10  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Split Q-reg
	vector value move contained in general registers.
Marcus Shawcroft - Sept. 25, 2012, 5:49 p.m.
On 10/09/12 16:05, Tejas Belagod wrote:
> 2012-09-10  Tejas Belagod<tejas.belagod@arm.com>
>
> gcc/
> 	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Split Q-reg
> 	vector value move contained in general registers.

Committed to aarch64-branch and aarch64-4.7-branch
/Marcus

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index d3f8ef2..1113b06 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -443,7 +443,7 @@ 
      case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>";
      case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]";
      case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1";
-     case 5: return "mov\t%0, %1;mov\t%H0, %H1";
+     case 5: return "#";
      case 6:
        {
 	int is_valid;
@@ -475,6 +475,27 @@ 
    (set_attr "length" "4,4,4,8,8,8,4")]
 )
 
+(define_split
+  [(set (match_operand:VQ 0 "register_operand" "")
+      (match_operand:VQ 1 "register_operand" ""))]
+  "TARGET_SIMD && reload_completed
+   && GP_REGNUM_P (REGNO (operands[0]))
+   && GP_REGNUM_P (REGNO (operands[1]))"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 2) (match_dup 3))]
+{
+  int rdest = REGNO (operands[0]);
+  int rsrc = REGNO (operands[1]);
+  rtx dest[2], src[2];
+
+  dest[0] = gen_rtx_REG (DImode, rdest);
+  src[0] = gen_rtx_REG (DImode, rsrc);
+  dest[1] = gen_rtx_REG (DImode, rdest + 1);
+  src[1] = gen_rtx_REG (DImode, rsrc + 1);
+
+  aarch64_simd_disambiguate_copy (operands, dest, src, 2);
+})
+
 (define_insn "orn<mode>3"
  [(set (match_operand:VDQ 0 "register_operand" "=w")
        (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))