[U-Boot] powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.

Submitted by Mark Marshall on Sept. 10, 2012, 9:06 a.m.

Details

Message ID 62d0a8de-3e39-4cc4-a49a-bc4faa49c6c2@mary.at.omicron.at
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Commit Message

Mark Marshall Sept. 10, 2012, 9:06 a.m.
We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
---
  arch/powerpc/cpu/mpc85xx/cpu.c |    5 +----
  1 files changed, 1 insertions(+), 4 deletions(-)

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diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index c1815e8..c0e54ad 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -267,10 +267,7 @@  reset_85xx_watchdog(void)
  	/*
  	 * Clear TSR(WIS) bit by writing 1
  	 */
-	unsigned long val;
-	val = mfspr(SPRN_TSR);
-	val |= TSR_WIS;
-	mtspr(SPRN_TSR, val);
+	mtspr(SPRN_TSR, TSR_WIS);
  }
  #endif	/* CONFIG_WATCHDOG */