From patchwork Sun Sep 9 21:04:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4ABDB2C0086 for ; Mon, 10 Sep 2012 09:09:18 +1000 (EST) Received: from localhost ([::1]:54242 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAokU-0001NF-Qv for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:08:58 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiQ-0006lx-MX for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoiO-0005uL-Cw for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:50 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiO-0005pQ-7Q for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:48 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=GS3k2JDNLkMaxM0QHu0hFsW0knWXoFXhyeYZgxU9UAg=; b=IBWiyNSdEN8uW7KuHouNavUwfFpSnM9n2sbT0OyiwqUcedZKUWcEMf1MJfm08VBUPW nVXCUT4yPj14Ekbf644O5AyucNQ9l2MK9zxo1RjiPhgRiCiqvSiCL4R8vUmEw9+nXxrw aCJ+yfZt/RaKLuC8wYG1CW9sJWFWcy3qYtB6QYpFPSI7DTnBULHex+RyzhDWWCVvlOah zRZ3b/Ak2risvKSV2n8F3IgGQI1lqpF9ibgw2iHj4oJGSI2eIVBzg8SPMUVB8wOuYYiz GXdCf/gQqpssmxwQl16c3WcexfkjU6reWjG9mELExKAQwvQ2NaHb+7wiLlnyKKXzH0PZ 2qGQ== Received: by 10.68.200.8 with SMTP id jo8mr2031514pbc.148.1347224807932; Sun, 09 Sep 2012 14:06:47 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.06.47 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:06:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:04:35 -0700 Message-Id: <1347224784-19472-18-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 017/126] target-s390: Convert LOAD, LOAD LOGICAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 20 +++++++++ target-s390x/translate.c | 100 ++++++++++++++++++--------------------------- 2 files changed, 60 insertions(+), 60 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 45c3913..2590f83 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -107,6 +107,26 @@ C(0xb9e7, XGRK, RRF_a, DO, r2, r3, r1, 0, xor, nz64) C(0xe382, XG, RXY_a, Z, r1, m2_64, r1, 0, xor, nz64) +/* LOAD */ + C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0) + C(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0) + C(0xe358, LY, RXY_a, Z, 0, a2, new, r1_32, ld32s, 0) + C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0) + C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0) + C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0) + C(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0) +/* LOAD IMMEDIATE */ + C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0) +/* LOAD RELATIVE LONG */ + C(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0) + C(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0) + C(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0) +/* LOAD LOGICAL */ + C(0xb916, LLGFR, RRE, Z, 0, r2_32u, 0, r1, mov2, 0) + C(0xe316, LLGF, RXY_a, Z, 0, a2, r1, 0, ld32u, 0) +/* LOAD LOGICAL RELATIVE LONG */ + C(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0) + /* MULTIPLY */ C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0) C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 01beb24..82dda8b 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1345,7 +1345,7 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) addr = get_address(s, x2, b2, d2); switch (op) { case 0x2: /* LTG R1,D2(X2,B2) [RXY] */ - case 0x4: /* lg r1,d2(x2,b2) */ + case 0x4: /* LG r1,d2(x2,b2) */ tcg_gen_qemu_ld64(regs[r1], addr, get_mem_index(s)); if (op == 0x2) { set_cc_s64(s, regs[r1]); @@ -1386,16 +1386,6 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) store_reg(r1, tmp2); tcg_temp_free_i64(tmp2); break; - case 0x14: /* LGF R1,D2(X2,B2) [RXY] */ - case 0x16: /* LLGF R1,D2(X2,B2) [RXY] */ - tmp2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); - if (op == 0x14) { - tcg_gen_ext32s_i64(tmp2, tmp2); - } - store_reg(r1, tmp2); - tcg_temp_free_i64(tmp2); - break; case 0x15: /* LGH R1,D2(X2,B2) [RXY] */ tmp2 = tcg_temp_new_i64(); tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s)); @@ -1449,12 +1439,6 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s)); tcg_temp_free_i64(tmp2); break; - case 0x58: /* LY R1,D2(X2,B2) [RXY] */ - tmp3 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(tmp3, addr, get_mem_index(s)); - store_reg32_i64(r1, tmp3); - tcg_temp_free_i64(tmp3); - break; case 0x71: /* LAY R1,D2(X2,B2) [RXY] */ store_reg(r1, addr); break; @@ -2919,9 +2903,6 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2) } tcg_temp_free_i64(tmp); break; - case 0x4: /* LGR R1,R2 [RRE] */ - store_reg(r1, regs[r2]); - break; case 0x6: /* LGBR R1,R2 [RRE] */ tmp2 = load_reg(r2); tcg_gen_ext8s_i64(tmp2, tmp2); @@ -2948,22 +2929,6 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2) tcg_temp_free_i64(tmp2); tcg_temp_free_i64(tmp3); break; - case 0x14: /* LGFR R1,R2 [RRE] */ - tmp32_1 = load_reg32(r2); - tmp = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp, tmp32_1); - store_reg(r1, tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i64(tmp); - break; - case 0x16: /* LLGFR R1,R2 [RRE] */ - tmp32_1 = load_reg32(r2); - tmp = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(tmp, tmp32_1); - store_reg(r1, tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i64(tmp); - break; case 0x17: /* LLGTR R1,R2 [RRE] */ tmp32_1 = load_reg32(r2); tmp = tcg_temp_new_i64(); @@ -3123,11 +3088,6 @@ static void disas_c0(DisasContext *s, int op, int r1, int i2) store_reg(r1, tmp); tcg_temp_free_i64(tmp); break; - case 0x1: /* LGFI R1,I2 [RIL] */ - tmp = tcg_const_i64((int64_t)i2); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; case 0x4: /* BRCL M1,I2 [RIL] */ /* m1 & (1 << (3 - cc)) */ tmp32_1 = tcg_const_i32(3); @@ -3343,13 +3303,6 @@ static void disas_s390_insn(DisasContext *s) set_cc_comp32(s, tmp32_1); tcg_temp_free_i32(tmp32_1); break; - case 0x18: /* LR R1,R2 [RR] */ - insn = ld_code2(s->pc); - decode_rr(s, insn, &r1, &r2); - tmp32_1 = load_reg32(r2); - store_reg32(r1, tmp32_1); - tcg_temp_free_i32(tmp32_1); - break; case 0x1d: /* DR R1,R2 [RR] */ insn = ld_code2(s->pc); decode_rr(s, insn, &r1, &r2); @@ -3513,18 +3466,6 @@ static void disas_s390_insn(DisasContext *s) tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp2); break; - case 0x58: /* l r1, d2(x2, b2) */ - insn = ld_code4(s->pc); - tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); - tmp2 = tcg_temp_new_i64(); - tmp32_1 = tcg_temp_new_i32(); - tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s)); - tcg_gen_trunc_i64_i32(tmp32_1, tmp2); - store_reg32(r1, tmp32_1); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i32(tmp32_1); - break; case 0x5d: /* D R1,D2(X2,B2) [RX] */ insn = ld_code4(s->pc); tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2); @@ -4427,6 +4368,33 @@ static ExitStatus op_and(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_ld32s(DisasContext *s, DisasOps *o) +{ + tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s)); + return NO_EXIT; +} + +static ExitStatus op_ld32u(DisasContext *s, DisasOps *o) +{ + tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s)); + return NO_EXIT; +} + +static ExitStatus op_ld64(DisasContext *s, DisasOps *o) +{ + tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s)); + return NO_EXIT; +} + +static ExitStatus op_mov2(DisasContext *s, DisasOps *o) +{ + o->out = o->in2; + o->g_out = o->g_in2; + TCGV_UNUSED_I64(o->in2); + o->g_in2 = false; + return NO_EXIT; +} + static ExitStatus op_mul(DisasContext *s, DisasOps *o) { tcg_gen_mul_i64(o->out, o->in1, o->in2); @@ -4566,6 +4534,11 @@ static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o) generally handled by having a "prep" generator install the TCG global as the destination of the operation. */ +static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o) +{ + store_reg(get_field(f, r1), o->out); +} + static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o) { store_reg32_i64(get_field(f, r1), o->out); @@ -4580,6 +4553,13 @@ static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o) store_reg32_i64(r1, o->out); } +static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o) +{ + if (get_field(f, r1) != get_field(f, r2)) { + store_reg32_i64(get_field(f, r1), o->out); + } +} + static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o) { tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));