From patchwork Sun Sep 9 21:05:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182732 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 30A612C0093 for ; Mon, 10 Sep 2012 09:07:39 +1000 (EST) Received: from localhost ([::1]:56812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAolU-0002iZ-Eo for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:10:00 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56812) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoj0-0008EL-9H for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoiz-000671-0L for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:26 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiy-0005pQ-QK for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:24 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=KU5N4DdCaV3J4rWjvAO5F3eI7vUgJBf1dfxmfX+kARo=; b=EGx9KZBZx5x0Bi5zclyG3KEzg11MDxZsgx5P/cnpYSESk7epVeR7OnyfJ+83XLVjcp 2lbyZNTAt46gZTeFYG/b40PMpY+oNjEuHqwnS32c1fIkCIUBKBPcX5r21P8FwJr/7zoP 9Rtr/2+Dg0Dc5zhA2B6T5BqyoL0bArI57HdpsrH9jPy8ISO+hF5QvaB3r/95HwjeeGGg 5GvnOCEPlTVDcqebdLgSg2bnvfAqlHiZE2+PkZLWq+ajx5c2iVyeDbBAESlcdTJ9WV4o 74z1IWxdQki/zqCHMjSnHcg5QYaOKt5QvB/97ZOZ2U+swF6Cxb/HdVdW62Q9obIAQzt8 YoNQ== Received: by 10.66.77.7 with SMTP id o7mr18107545paw.37.1347224844548; Sun, 09 Sep 2012 14:07:24 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.23 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:17 -0700 Message-Id: <1347224784-19472-60-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 059/126] target-s390: Convert EFPC, STFPC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 6 ++++++ target-s390x/translate.c | 38 +++++++++++++------------------------- 2 files changed, 19 insertions(+), 25 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 95f9987..745d1e6 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -175,6 +175,9 @@ /* EXECUTE RELATIVE LONG */ C(0xc600, EXRL, RIL_b, EE, r1_o, ri2, 0, 0, ex, 0) +/* EXTRACT FPC */ + C(0xb38c, EFPC, RRE, Z, 0, 0, new, r1_32, efpc, 0) + /* INSERT CHARACTER */ C(0x4300, IC, RX_a, Z, 0, m2_8u, 0, r1_8, mov2, 0) C(0xe373, ICY, RXY_a, LD, 0, m2_8u, 0, r1_8, mov2, 0) @@ -395,6 +398,9 @@ /* STORE HALFWORD RELATIVE LONG */ C(0xc407, STHRL, RIL_b, GIE, r1_o, ri2, 0, 0, st16, 0) +/* STORE FPC */ + C(0xb29c, STFPC, S, Z, 0, a2, new, m2_32, efpc, 0) + /* STORE MULTIPLE */ D(0x9000, STM, RS_a, Z, 0, a2, 0, 0, stm, 0, 4) D(0xeb90, STMY, RSY_a, LD, 0, a2, 0, 0, stm, 0, 4) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 698cb99..439a90d 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1833,12 +1833,6 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2) tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc)); tcg_temp_free_i32(tmp32_1); break; - case 0x8c: /* EFPC R1 [RRE] */ - tmp32_1 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc)); - store_reg32(r1, tmp32_1); - tcg_temp_free_i32(tmp32_1); - break; case 0x94: /* CEFBR R1,R2 [RRE] */ case 0x95: /* CDFBR R1,R2 [RRE] */ case 0x96: /* CXFBR R1,R2 [RRE] */ @@ -1990,7 +1984,7 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2) static void disas_s390_insn(DisasContext *s) { - TCGv_i64 tmp, tmp2; + TCGv_i64 tmp; TCGv_i32 tmp32_1, tmp32_2; unsigned char opc; uint64_t insn; @@ -2003,24 +1997,7 @@ static void disas_s390_insn(DisasContext *s) case 0xb2: insn = ld_code4(s->pc); op = (insn >> 16) & 0xff; - switch (op) { - case 0x9c: /* STFPC D2(B2) [S] */ - d2 = insn & 0xfff; - b2 = (insn >> 12) & 0xf; - tmp32_1 = tcg_temp_new_i32(); - tmp = tcg_temp_new_i64(); - tmp2 = get_address(s, 0, b2, d2); - tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc)); - tcg_gen_extu_i32_i64(tmp, tmp32_1); - tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s)); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; - default: - disas_b2(s, op, insn); - break; - } + disas_b2(s, op, insn); break; case 0xb3: insn = ld_code4(s->pc); @@ -2723,6 +2700,12 @@ static ExitStatus op_divu64(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_efpc(DisasContext *s, DisasOps *o) +{ + tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc)); + return NO_EXIT; +} + static ExitStatus op_ex(DisasContext *s, DisasOps *o) { /* ??? Perhaps a better way to implement EXECUTE is to set a bit in @@ -3620,6 +3603,11 @@ static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o) tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s)); } +static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o) +{ + tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s)); +} + /* ====================================================================== */ /* The "INput 1" generators. These load the first operand to an insn. */