From patchwork Sun Sep 9 21:04:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C8FF02C0084 for ; Mon, 10 Sep 2012 08:32:44 +1000 (EST) Received: from localhost ([::1]:53824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAok5-00019q-Tq for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:08:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiV-000719-Ow for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoiR-0005vW-Qg for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:55 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiR-0005pQ-La for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:51 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=x4FlzdQ0hT337vdn3rlJzaRw2bTYGla8woFDYM9KrRY=; b=EQfA3eaJqUhzpV7s/jXuDhygRnqPJkSr0341uG876MsjtIEt9jnSlubBYq+gaQ6Rtu nTG/yvqnABsYQXD1N2F1tUUTBMm3MYHDu/5+dlQ9ZMOY1LOF8s+Se20IY+rSICMP4SS4 bKFN3gSkxqBfiJ9BY6lGxkdLgTb77r5HpMJS5VJopLeE2z8+Gdt5db1/LvlBr2LHIVPJ m4jU7fO7s7lHFjD4cKoyDTg03tDhUeW18cwSTBC78Chjdxk6DnfrbBRA1RVDLwpSlPQx bJ2nGwo8md7yrvBg5+huU2t1nBeL3kGdkHWtAZorI0mCoZXekbZQoBqnUp+SMVM4TfHQ a66g== Received: by 10.68.218.72 with SMTP id pe8mr2067574pbc.33.1347224811412; Sun, 09 Sep 2012 14:06:51 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.06.50 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:06:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:04:39 -0700 Message-Id: <1347224784-19472-22-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 021/126] target-s390: Convert LOAD LOGICAL IMMEDIATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 7 +++++++ target-s390x/translate.c | 42 ++++++++++++------------------------------ 2 files changed, 19 insertions(+), 30 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 06d0ad8..9433d3d 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -168,6 +168,13 @@ /* LOAD LOGICAL HALFWORD RELATIVE LONG */ C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0) C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0) +/* LOAD LOGICAL IMMEDATE */ + D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32) + D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0) + D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48) + D(0xa50d, LLIHL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 32) + D(0xa50e, LLILH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 16) + D(0xa50f, LLILL, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 0) /* MULTIPLY */ C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 1c83009..8233bed 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2026,26 +2026,6 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) tcg_temp_free_i32(tmp32); tcg_temp_free_i64(tmp); break; - case 0xc: /* LLIHH R1,I2 [RI] */ - tmp = tcg_const_i64( ((uint64_t)i2) << 48 ); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xd: /* LLIHL R1,I2 [RI] */ - tmp = tcg_const_i64( ((uint64_t)i2) << 32 ); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xe: /* LLILH R1,I2 [RI] */ - tmp = tcg_const_i64( ((uint64_t)i2) << 16 ); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xf: /* LLILL R1,I2 [RI] */ - tmp = tcg_const_i64(i2); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; default: LOG_DISAS("illegal a5 operation 0x%x\n", op); gen_illegal_opcode(s); @@ -3027,16 +3007,6 @@ static void disas_c0(DisasContext *s, int op, int r1, int i2) tcg_temp_free_i64(tmp); tcg_temp_free_i32(tmp32_1); break; - case 0xe: /* LLIHF R1,I2 [RIL] */ - tmp = tcg_const_i64(((uint64_t)(uint32_t)i2) << 32); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; - case 0xf: /* LLILF R1,I2 [RIL] */ - tmp = tcg_const_i64((uint32_t)i2); - store_reg(r1, tmp); - tcg_temp_free_i64(tmp); - break; default: LOG_DISAS("illegal c0 operation 0x%x\n", op); gen_illegal_opcode(s); @@ -4682,6 +4652,18 @@ static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o) o->in2 = tcg_const_i64((uint32_t)get_field(f, i2)); } +static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o) +{ + uint64_t i2 = (uint16_t)get_field(f, i2); + o->in2 = tcg_const_i64(i2 << s->insn->data); +} + +static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o) +{ + uint64_t i2 = (uint32_t)get_field(f, i2); + o->in2 = tcg_const_i64(i2 << s->insn->data); +} + /* ====================================================================== */ /* Find opc within the table of insns. This is formulated as a switch