From patchwork Sun Sep 9 21:04:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 78D112C0095 for ; Mon, 10 Sep 2012 08:04:37 +1000 (EST) Received: from localhost ([::1]:54243 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoka-0001NH-FQ for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:09:04 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoii-0007eX-HE for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoig-00060Y-FP for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:08 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoig-0005pQ-91 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:06 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:07:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=ac7qXiHqFEPWmW/WGvNqqE42N5OYNP02t37BfxfQTbg=; b=FxdA6+fLnpELCklVLI6PPY+zbQGJCRDkASZqsqSLTHMs4xdC/I0+QSyrW4sfZHbSNO ppl5C3TNIdXW5nOQ2jb/dzHKbqRCozO3GhFuOtyKXnk7ghQr4MBmma/yg8b2gWPbx539 qsoSwNB1uAHOy8DcDZ/2hYdQWfgyFo43xfsTOPDB0qmp/B+VPFwLCbXfcGxbbF1wccqZ sB0MwrALXvvnY5P8KMwUIPn6oCe123avcBNnmWtgPND6blsJN6YizHonbTXZ8mgYl3Bj 4NXqyDYS4cDRLQjFYuovHrmkUVCbzbdKBHYgEMNA74UEKWoz1/y/XgDIi5SmR1thYgfD K7Ug== Received: by 10.66.83.166 with SMTP id r6mr18172424pay.25.1347224826013; Sun, 09 Sep 2012 14:07:06 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.05 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:04:56 -0700 Message-Id: <1347224784-19472-39-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 038/126] target-s390: Convert INSERT CHARACTERS UNDER MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Change the CC handling to be more like TEST UNDER MASK, with val & mask. This lets us handle ICMH much more like ICM. Signed-off-by: Richard Henderson --- target-s390x/cc_helper.c | 31 +++-------- target-s390x/helper.h | 1 - target-s390x/insn-data.def | 4 ++ target-s390x/mem_helper.c | 33 ----------- target-s390x/translate.c | 136 +++++++++++++++++++++------------------------ 5 files changed, 74 insertions(+), 131 deletions(-) diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index 663d0c9..d13f241 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -331,35 +331,18 @@ static uint32_t cc_calc_comp_32(int32_t dst) } /* calculate condition code for insert character under mask insn */ -static uint32_t cc_calc_icm_32(uint32_t mask, uint32_t val) +static uint32_t cc_calc_icm(uint64_t mask, uint64_t val) { - uint32_t cc; - - HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val); - if (mask == 0xf) { - if (!val) { - return 0; - } else if (val & 0x80000000) { + if ((val & mask) == 0) { + return 0; + } else { + int top = clz64(mask); + if ((int64_t)(val << top) < 0) { return 1; } else { return 2; } } - - if (!val || !mask) { - cc = 0; - } else { - while (mask != 1) { - mask >>= 1; - val >>= 8; - } - if (val & 0x80) { - cc = 1; - } else { - cc = 2; - } - } - return cc; } static uint32_t cc_calc_slag(uint64_t src, uint64_t shift) @@ -488,7 +471,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, break; case CC_OP_ICM: - r = cc_calc_icm_32(src, dst); + r = cc_calc_icm(src, dst); break; case CC_OP_SLAG: r = cc_calc_slag(src, dst); diff --git a/target-s390x/helper.h b/target-s390x/helper.h index 56e1b60..93931e4 100644 --- a/target-s390x/helper.h +++ b/target-s390x/helper.h @@ -38,7 +38,6 @@ DEF_HELPER_FLAGS_1(nabs_i32, TCG_CALL_PURE|TCG_CALL_CONST, s32, s32) DEF_HELPER_FLAGS_1(abs_i64, TCG_CALL_PURE|TCG_CALL_CONST, i64, s64) DEF_HELPER_FLAGS_1(nabs_i64, TCG_CALL_PURE|TCG_CALL_CONST, s64, s64) DEF_HELPER_4(stcmh, void, env, i32, i64, i32) -DEF_HELPER_4(icmh, i32, env, i32, i64, i32) DEF_HELPER_3(ipm, void, env, i32, i32) DEF_HELPER_4(stam, void, env, i32, i64, i32) DEF_HELPER_4(lam, void, env, i32, i64, i32) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 7fff688..322fcc1 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -160,6 +160,10 @@ /* INSERT CHARACTER */ C(0x4300, IC, RX_a, Z, 0, m2_8u, 0, r1_8, mov2, 0) C(0xe373, ICY, RXY_a, LD, 0, m2_8u, 0, r1_8, mov2, 0) +/* INSERT CHARACTERS UNDER MASK */ + D(0xbf00, ICM, RS_b, Z, 0, a2, r1, 0, icm, 0, 0) + D(0xeb81, ICMY, RSY_b, LD, 0, a2, r1, 0, icm, 0, 0) + D(0xeb80, ICMH, RSY_b, Z, 0, a2, r1, 0, icm, 0, 32) /* INSERT IMMEDIATE */ D(0xc008, IIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2020) D(0xc009, IILF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2000) diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index b21b37c..b868346 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -635,39 +635,6 @@ void HELPER(stcmh)(CPUS390XState *env, uint32_t r1, uint64_t address, } } -/* insert character under mask high; same as icm, but operates on the - upper half of r1 */ -uint32_t HELPER(icmh)(CPUS390XState *env, uint32_t r1, uint64_t address, - uint32_t mask) -{ - int pos = 56; /* top of the upper half of r1 */ - uint64_t rmask = 0xff00000000000000ULL; - uint8_t val = 0; - int ccd = 0; - uint32_t cc = 0; - - while (mask) { - if (mask & 8) { - env->regs[r1] &= ~rmask; - val = cpu_ldub_data(env, address); - if ((val & 0x80) && !ccd) { - cc = 1; - } - ccd = 1; - if (val && cc == 0) { - cc = 2; - } - env->regs[r1] |= (uint64_t)val << pos; - address++; - } - mask = (mask << 1) & 0xf; - pos -= 8; - rmask >>= 8; - } - - return cc; -} - /* load access registers r1 to r3 from memory at a2 */ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 4f7731a..e9eae6f 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -32,6 +32,7 @@ #include "disas.h" #include "tcg-op.h" #include "qemu-log.h" +#include "host-utils.h" /* global register indexes */ static TCGv_ptr cpu_env; @@ -559,11 +560,6 @@ static inline void set_cc_s64(DisasContext *s, TCGv_i64 val) gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val); } -static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2) -{ - gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2); -} - static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2) { tcg_gen_extu_i32_i64(cc_src, v1); @@ -894,7 +890,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_LTGT0_64: case CC_OP_NZ: - case CC_OP_ICM: c->u.s64.a = cc_dst; c->u.s64.b = tcg_const_i64(0); c->g1 = true; @@ -908,6 +903,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_TM_32: case CC_OP_TM_64: + case CC_OP_ICM: c->u.s64.a = tcg_temp_new_i64(); c->u.s64.b = tcg_const_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); @@ -1517,18 +1513,6 @@ do_mh: tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp2); break; - case 0x80: /* ICMH R1,M3,D2(B2) [RSY] */ - tmp = get_address(s, 0, b2, d2); - tmp32_1 = tcg_const_i32(r1); - tmp32_2 = tcg_const_i32(r3); - potential_page_fault(s); - /* XXX split CC calculation out */ - gen_helper_icmh(cc_op, cpu_env, tmp32_1, tmp, tmp32_2); - set_cc_static(s); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - break; default: LOG_DISAS("illegal eb operation 0x%x\n", op); gen_illegal_opcode(s); @@ -2354,7 +2338,7 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2) static void disas_s390_insn(DisasContext *s) { TCGv_i64 tmp, tmp2, tmp3, tmp4; - TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4; + TCGv_i32 tmp32_1, tmp32_2; unsigned char opc; uint64_t insn; int op, r1, r2, r3, d1, d2, x2, b1, b2, i, i2, r1b; @@ -2777,60 +2761,6 @@ static void disas_s390_insn(DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0xbf: /* ICM R1,M3,D2(B2) [RS] */ - insn = ld_code4(s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - if (r3 == 15) { - /* effectively a 32-bit load */ - tmp = get_address(s, 0, b2, d2); - tmp32_1 = tcg_temp_new_i32(); - tmp32_2 = tcg_const_i32(r3); - tcg_gen_qemu_ld32u(tmp, tmp, get_mem_index(s)); - store_reg32_i64(r1, tmp); - tcg_gen_trunc_i64_i32(tmp32_1, tmp); - set_cc_icm(s, tmp32_2, tmp32_1); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - } else if (r3) { - uint32_t mask = 0x00ffffffUL; - uint32_t shift = 24; - int m3 = r3; - tmp = get_address(s, 0, b2, d2); - tmp2 = tcg_temp_new_i64(); - tmp32_1 = load_reg32(r1); - tmp32_2 = tcg_temp_new_i32(); - tmp32_3 = tcg_const_i32(r3); - tmp32_4 = tcg_const_i32(0); - while (m3) { - if (m3 & 8) { - tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); - tcg_gen_trunc_i64_i32(tmp32_2, tmp2); - if (shift) { - tcg_gen_shli_i32(tmp32_2, tmp32_2, shift); - } - tcg_gen_andi_i32(tmp32_1, tmp32_1, mask); - tcg_gen_or_i32(tmp32_1, tmp32_1, tmp32_2); - tcg_gen_or_i32(tmp32_4, tmp32_4, tmp32_2); - tcg_gen_addi_i64(tmp, tmp, 1); - } - m3 = (m3 << 1) & 0xf; - mask = (mask >> 8) | 0xff000000UL; - shift -= 8; - } - store_reg32(r1, tmp32_1); - set_cc_icm(s, tmp32_3, tmp32_4); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - tcg_temp_free_i32(tmp32_3); - tcg_temp_free_i32(tmp32_4); - } else { - /* i.e. env->cc = 0 */ - gen_op_movi_cc(s, 0); - } - break; case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */ case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */ case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */ @@ -3440,6 +3370,66 @@ static ExitStatus op_divu64(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_icm(DisasContext *s, DisasOps *o) +{ + int m3 = get_field(s->fields, m3); + int pos, len, base = s->insn->data; + TCGv_i64 tmp = tcg_temp_new_i64(); + uint64_t ccm; + + switch (m3) { + case 0xf: + /* Effectively a 32-bit load. */ + tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s)); + len = 32; + goto one_insert; + + case 0xc: + case 0x6: + case 0x3: + /* Effectively a 16-bit load. */ + tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s)); + len = 16; + goto one_insert; + + case 0x8: + case 0x4: + case 0x2: + case 0x1: + /* Effectively an 8-bit load. */ + tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s)); + len = 8; + goto one_insert; + + one_insert: + pos = base + ctz32(m3) * 8; + tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len); + ccm = ((1ull << len) - 1) << pos; + break; + + default: + /* This is going to be a sequence of loads and inserts. */ + pos = base + 32 - 8; + ccm = 0; + while (m3) { + if (m3 & 0x8) { + tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s)); + tcg_gen_addi_i64(o->in2, o->in2, 1); + tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8); + ccm |= 0xff << pos; + } + m3 = (m3 << 1) & 0xf; + pos -= 8; + } + break; + } + + tcg_gen_movi_i64(tmp, ccm); + gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out); + tcg_temp_free_i64(tmp); + return NO_EXIT; +} + static ExitStatus op_insi(DisasContext *s, DisasOps *o) { int shift = s->insn->data & 0xff;