From patchwork Sun Sep 9 21:04:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 78CB62C0089 for ; Mon, 10 Sep 2012 08:00:53 +1000 (EST) Received: from localhost ([::1]:53464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAojx-0000xx-4m for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:08:25 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiK-0006U7-H2 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoiI-0005sM-Qf for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:44 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiI-0005pQ-Kl for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:06:42 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=kFj1d/9W8OVEYXNproUss4dD2797wBdta1zBzdQhAfU=; b=HIou+ORhq/mXUUdebHAfmoYkSsdCHQjuQ+z4lY9R+1fWOQA5CsihldTH0Xl1KeHqXO F55CBRln0AMAj8Kiite8T9mRZMKgWUIeEVrUlzirhgSQiJEtZk/T7prNuxJHKYKgwCfW NNRC+LfttwlyxiR8ygE+jtUczvkoiVZNEtrwQ82w1pFsD0kW+W1NvS0l1rgcV6zrywZI AWHmvuq2vtgbOTdLy+52v5LYL0Sa04+th/PJ/3GOlcwyIXmptJgJ6Lq0UNw8X0GR08Hv TRxS33Q9vIJUZ4YpVLfwmxP/5TWlObfdqIyAoFjCZL5Z+rKuphmJnERnAy85Mtwjx0jI yHYQ== Received: by 10.66.83.129 with SMTP id q1mr18249581pay.4.1347224802374; Sun, 09 Sep 2012 14:06:42 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.06.41 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:06:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:04:29 -0700 Message-Id: <1347224784-19472-12-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 011/126] target-s390: Convert ADD HALFWORD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 7 +++++++ target-s390x/translate.c | 43 +++++++------------------------------------ 2 files changed, 14 insertions(+), 36 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 7d81928..2acc8f0 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -15,6 +15,13 @@ C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64) C(0xeb7a, AGSI, SIY, GIE, m1_64, i2, new, m1_64, add, adds64) C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64) +/* ADD HALFWORD */ + C(0x4a00, AH, RX_a, Z, r1, m2_16s, new, r1_32, add, adds32) + C(0xe37a, AHY, RXY_a, LD, r1, m2_16s, new, r1_32, add, adds32) +/* ADD HALFWORD IMMEDIATE */ + C(0xa70a, AHI, RI_a, Z, r1, i2, new, r1_32, add, adds32) + C(0xa70b, AGHI, RI_a, Z, r1, i2, r1, 0, add, adds64) + /* ADD LOGICAL */ C(0x1e00, ALR, RR_a, Z, r1, r2, new, r1_32, add, addu32) C(0xb9fa, ALRK, RRF_a, DO, r2, r3, new, r1_32, add, addu32) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 70e5d87..5850b23 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -557,11 +557,6 @@ static inline void set_cc_s64(DisasContext *s, TCGv_i64 val) gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val); } -static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr) -{ - gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr); -} - static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr) { @@ -2259,7 +2254,7 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) static void disas_a7(DisasContext *s, int op, int r1, int i2) { TCGv_i64 tmp, tmp2; - TCGv_i32 tmp32_1, tmp32_2, tmp32_3; + TCGv_i32 tmp32_1; int l1; LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2); @@ -2334,36 +2329,6 @@ static void disas_a7(DisasContext *s, int op, int r1, int i2) store_reg(r1, tmp); tcg_temp_free_i64(tmp); break; - case 0xa: /* AHI R1,I2 [RI] */ - tmp32_1 = load_reg32(r1); - tmp32_2 = tcg_temp_new_i32(); - tmp32_3 = tcg_const_i32(i2); - - if (i2 < 0) { - tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2); - } else { - tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3); - } - - store_reg32(r1, tmp32_2); - set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2); - tcg_temp_free_i32(tmp32_1); - tcg_temp_free_i32(tmp32_2); - tcg_temp_free_i32(tmp32_3); - break; - case 0xb: /* aghi r1, i2 */ - tmp = load_reg(r1); - tmp2 = tcg_const_i64(i2); - - if (i2 < 0) { - tcg_gen_subi_i64(regs[r1], tmp, -i2); - } else { - tcg_gen_add_i64(regs[r1], tmp, tmp2); - } - set_cc_add64(s, tmp, tmp2, regs[r1]); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; case 0xc: /* MHI R1,I2 [RI] */ tmp32_1 = load_reg32(r1); tcg_gen_muli_i32(tmp32_1, tmp32_1, i2); @@ -5059,6 +5024,12 @@ static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o) o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2)); } +static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o) +{ + in2_a2(s, f, o); + tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s)); +} + static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o) { in2_a2(s, f, o);