From patchwork Sun Sep 9 21:05:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 72B8B2C0089 for ; Mon, 10 Sep 2012 07:49:11 +1000 (EST) Received: from localhost ([::1]:58050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAolp-0003OQ-DQ for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:10:21 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAojW-0000K4-4K for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAojV-0006Hj-5w for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:58 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:63857) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAojV-0005xl-07 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:57 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so292285pbb.4 for ; Sun, 09 Sep 2012 14:07:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=T83O8Q05D3qflsJi3N2OQoXB5TcXjuyY6FQMKCTEE/Y=; b=f7kLjgLu+RT+X0Uqa8rjv5nCG1EgZ+eTLVEWKNy/yEWNXiZb2cEpoCEmJUW097ta/J XJtCQ7KHfOFOY6uYBor9VgVzKDhxj0p4YCX8H/kUGT/+8qx2z7o+mJsie5Z8z3y/8FA/ GnTlXmgb76x06YvQkqdGG69oz1UZCREbn8aXmZXfv5+zEmo7n3gtvghlTuQfFfdUCJed tFv11umglz/c5NpWzcrnrOa7OI4xVieNVl/MeadwxfIGrU10TXS2vH+7ToYqsjEaFeyJ QnOUShi3Pe5ugTbKsgLksZEHLwfyrbBDmLQM7SwXobU+zcNe4+3gtgkkYEok7bMyy8R8 cuDA== Received: by 10.66.72.130 with SMTP id d2mr18062860pav.59.1347224876761; Sun, 09 Sep 2012 14:07:56 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.55 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:54 -0700 Message-Id: <1347224784-19472-97-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 096/126] target-s390: Convert STAP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 2 ++ target-s390x/translate.c | 24 ++++++++++-------------- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 63da5ab..6638453 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -658,6 +658,8 @@ /* STORE CONTROL */ C(0xb600, STCTL, RS_a, Z, 0, a2, 0, 0, stctl, 0) C(0xeb25, STCTG, RSY_a, Z, 0, a2, 0, 0, stctg, 0) +/* STORE CPU ADDRESS */ + C(0xb212, STAP, S, Z, la2, 0, new, m1_16, stap, 0) /* STORE CPU ID */ C(0xb202, STIDP, S, Z, la2, 0, new, m1_64, stidp, 0) /* STORE CPU TIMER */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 6b60de1..873e08c 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1030,20 +1030,6 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn) LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2); switch (op) { - case 0x12: /* STAP D2(B2) [S] */ - /* Store CPU Address */ - check_privileged(s); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp2 = tcg_temp_new_i64(); - tmp32_1 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, cpu_num)); - tcg_gen_extu_i32_i64(tmp2, tmp32_1); - tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s)); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i32(tmp32_1); - break; case 0x21: /* IPTE R1,R2 [RRE] */ /* Invalidate PTE */ check_privileged(s); @@ -2798,6 +2784,16 @@ static ExitStatus op_ssm(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_stap(DisasContext *s, DisasOps *o) +{ + check_privileged(s); + /* ??? Surely cpu address != cpu number. In any case the previous + version of this stored more than the required half-word, so it + is unlikely this has ever been tested. */ + tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); + return NO_EXIT; +} + static ExitStatus op_stctl(DisasContext *s, DisasOps *o) { TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));