Patchwork [U-Boot] powerpc mpc85xx: Synchronization Required for mmucsr0 spr

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Submitter Laurent Joye
Date Sept. 7, 2012, 12:52 p.m.
Message ID <6670B5959A1255459E98630A607295B473CC2E@hrsrv31.haslerrail.net>
Download mbox | patch
Permalink /patch/182376/
State Superseded, archived
Delegated to: Andy Fleming
Headers show

Comments

Laurent Joye - Sept. 7, 2012, 12:52 p.m.
As explained in the PowerPC e500 Core Family Reference Manual
(Synchronization Requirements for SPRs), an isync instruction
is required after a mtspr mmucsr0 instruction.

Signed-off-by: Laurent Joye <laurent.joye@haslerrail.com>
---
 arch/powerpc/cpu/mpc85xx/tlb.c |    1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c
b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..c548f67 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -38,6 +38,7 @@  void invalidate_tlb(u8 tlb)
                mtspr(MMUCSR0, 0x4);
        if (tlb == 1)
                mtspr(MMUCSR0, 0x2);
+       asm volatile("isync");
 }
 
 void init_tlbs(void)